公开(公告)号：US20120284464A1

公开(公告)日：2012-11-08

申请号：US13461902

申请日：2012-05-02

申请人： Gururaj PADAKI ,  Anindya SAHA ,  Parag NAIK ,  Vishwakumara KAYARGADDE ,  Sunil Hosur Ramesh

发明人： Gururaj PADAKI ,  Anindya SAHA ,  Parag NAIK ,  Vishwakumara KAYARGADDE ,  Sunil Hosur Ramesh

IPC分类号： G06F12/00

CPC分类号： G06F7/483

摘要： A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

摘要翻译： 提供了一种用于通过检测中央处理单元中的输入信号的动态范围来计算块浮点缩放因子的系统，而没有额外的开销周期。 该系统包括动态范围监测单元，其通过窥探输出写入数据和输入信号的输入存储器读取数据来检测输入信号的动态范围。 动态范围监视单元包括运行的最大计数单元，其存储前导零和前导零的计数的最小值，以及存储尾随零计数的最小值的运行最小计数。 基于前导零和前导零的计数的最小值和尾随零的计数来检测动态范围。 该系统还包括一个缩放因子计算模块，它根据动态范围计算块浮点（BFP）缩放因子。

公开(公告)号：US20120249888A1

公开(公告)日：2012-10-04

申请号：US13435326

申请日：2012-03-30

申请人： Parag NAIK ,  Anindya SAHA ,  Hemant MALLAPUR ,  Sunil HR ,  Gururaj PADAKI

发明人： Parag NAIK ,  Anindya SAHA ,  Hemant MALLAPUR ,  Sunil HR ,  Gururaj PADAKI

IPC分类号： H04N5/455

CPC分类号： H04B1/0007 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/27 ,  H03M13/2906 ,  H03M13/2936 ,  H03M13/6522 ,  H04H40/18 ,  H04N5/455 ,  H04N5/46 ,  H04N21/2383 ,  H04N21/4382

摘要： A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

摘要翻译： 能够支持用于输入信号的调制，解调和转换的多种通信标准和平台的软件定义无线电（SDR）子系统。 SDR子系统包括信号调节簇（SCC）单元，其包括适于基于采样的信号处理的信号调节CPU，包括适用于基于块的信号处理的信号处理CPU的信号处理簇（SPC）单元，以及信道编解码器 集群（CCC）单元执行信道编码或信道解码操作。

公开(公告)号：US20120284318A1

公开(公告)日：2012-11-08

申请号：US13462116

申请日：2012-05-02

申请人： Parag NAIK ,  Anindya SAHA ,  Gururaj PADAKI ,  Subrahmanya Kondageri SHANKARAIAH ,  Saurabh MISHRA

发明人： Parag NAIK ,  Anindya SAHA ,  Gururaj PADAKI ,  Subrahmanya Kondageri SHANKARAIAH ,  Saurabh MISHRA

IPC分类号： G06F17/10

CPC分类号： H03H21/0012 ,  H03H2021/007 ,  H03H2021/0072 ,  H03H2218/10

摘要： A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

摘要翻译： 提供一种实现数字滤波器的方法。 该方法包括（a）通过测量输入数据样本的前导零或一个之间的距离以及输入数据样本的尾随零来确定输入信号的输入数据样本的位宽。 输入数据样本是通过以预定义的时间间隔对输入信号进行采样而获得的，（b）基于输入数据样本的位宽的第一概率分布函数（PDF））获得具有可变位宽的位宽乘数 ，（c）基于输入数据样本的位宽和滤波器系数的位宽分配输入数据样本和滤波器系数到位宽乘法器的一个位宽倍数，以及（d） 在一个位宽乘数上执行乘法和累加（MAC）运算的乘法运算，以产生数字滤波器的输出。

公开(公告)号：US20120284487A1

公开(公告)日：2012-11-08

申请号：US13462144

申请日：2012-05-02

申请人： Anindya SAHA ,  Gururaj PADAKI ,  Santosh BILLAVA ,  Rakesh A. JOSHI

发明人： Anindya SAHA ,  Gururaj PADAKI ,  Santosh BILLAVA ,  Rakesh A. JOSHI

IPC分类号： G06F15/76 ,  G06F9/302

CPC分类号： G06F9/3887 ,  G06F7/552 ,  G06F7/586 ,  G06F9/3001 ,  G06F9/30109 ,  G06F9/3893 ,  G06F15/8053 ,  G06F15/8076 ,  G06F2207/3828 ,  G06F2207/5523 ,  H04L25/03019 ,  H04L27/0008

摘要： A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one or more n-way signal registers that receive the high speed streaming inputs, one or more n-way coefficient registers that store filter coefficients for the multiple signal processing, and one or more n-way Multiply and Accumulate (MAC) units that receive the high speed streaming inputs from the one or more n-way signal registers and filter coefficients from one or more n-way coefficient registers. The one or more n-way MAC units perform a vertical MAC operation and a horizontal multiply and add operation on the high speed streaming inputs.

摘要翻译： 提供了能够支持用于多个解调标准的多个信号处理操作的向量时隙处理器。 矢量时隙处理器包括对高速流输入进行多信号处理操作的多个微执行时隙（MES）。 每个MES包括接收高速流输入的一个或多个n路信号寄存器，存储多信号处理的滤波器系数的一个或多个n路系数寄存器和一个或多个n路乘法和累加（ MAC）单元，其从一个或多个n路信号寄存器接收高速流输入和来自一个或多个n路系数寄存器的滤波器系数。 一个或多个n路MAC单元在高速流输入上执行垂直MAC操作和水平乘法和相加操作。

公开(公告)号：US20050091562A1

公开(公告)日：2005-04-28

申请号：US10710451

申请日：2004-07-12

申请人： Nikila KRISHNAMOORTHY ,  Anindya SAHA ,  Rubin PAREKHJI

发明人： Nikila KRISHNAMOORTHY ,  Anindya SAHA ,  Rubin PAREKHJI

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318563

摘要： Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsystem module”) may be implemented to be tested with any of a multiple characteristics of a control signal, and a register which is programmable to generate a derived control signal of a desired characteristic from an original control signal, is provided. The derived control signal is provided to test the subsystem module. According to an aspect of the invention the desired characteristic may be determined, for example, to test a path between the two modules at the same speed as at which the path would be operated in a functional mode.

摘要翻译： 在不同模块以不同控制信号的特性运行的情况下，集成电路（例如芯片单元（SOC）中的系统）中的模块（例如知识产权（IP）核心）的测试。 在一个实施例中，另一个模块（“子系统模块”）可以被实现为用控制信号的多个特性中的任何一个进行测试，以及寄存器，其被编程以从原始控制信号产生所需特性的导出控制信号 ，被提供。 提供导出的控制信号以测试子系统模块。 根据本发明的一个方面，可以确定期望的特性，例如，以与功能模式下操作路径相同的速度来测试两个模块之间的路径。

公开(公告)号：US20050057230A1

公开(公告)日：2005-03-17

申请号：US10710861

申请日：2004-08-09

申请人： Anindya SAHA ,  Vivek PAWAR ,  Sudheer PRASAD ,  Anmol SHARMA ,  Suresh PUTHUCODE

发明人： Anindya SAHA ,  Vivek PAWAR ,  Sudheer PRASAD ,  Anmol SHARMA ,  Suresh PUTHUCODE

IPC分类号： G05F1/46 ,  G05F1/575 ,  G05F3/02

CPC分类号： G06F1/26 ,  G11C5/06

摘要： A characteristic is measured on multiple portions of an integrated circuit, and the supply voltage adjusted based on the measurements. In an embodiment, the characteristic corresponds to propagation delay which indicates whether the integrated circuit is implemented with a strong, weak or nominal process corner. In general, the supply voltage can be increased in the case of a weak process corner and decreased in the case of a strong process corner.

摘要翻译： 在集成电路的多个部分上测量特性，并且基于测量调整电源电压。 在一个实施例中，特性对应于传播延迟，其指示集成电路是用强的，弱的还是标称的工艺角来实现的。 通常，在过程拐角较弱的情况下，电源电压可以增加，而在过程拐角较强的情况下，电源电压可以提高。