公开(公告)号：US20230360712A1

公开(公告)日：2023-11-09

申请号：US17736564

申请日：2022-05-04

申请人： ALEXANDER LOUIS BRAUN ,  MAX E. NIELSEN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  HAITAO O. DAI ,  CHARLES RYAN WALLACE

发明人： ALEXANDER LOUIS BRAUN ,  MAX E. NIELSEN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  HAITAO O. DAI ,  CHARLES RYAN WALLACE

IPC分类号： H03L7/081 ,  H03L7/08 ,  H03K19/195 ,  H03K3/037

CPC分类号： H03L7/0816 ,  H03L7/0805 ,  H03K19/195 ,  H03K3/037

摘要： Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

公开(公告)号：US20230359915A1

公开(公告)日：2023-11-09

申请号：US17736646

申请日：2022-05-04

申请人： HAITAO O. DAI ,  MAX E. NIELSEN ,  ALEXANDER LOUIS BRAUN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  CHARLES RYAN WALLACE

发明人： HAITAO O. DAI ,  MAX E. NIELSEN ,  ALEXANDER LOUIS BRAUN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  CHARLES RYAN WALLACE

IPC分类号： G06N10/40 ,  G01R33/035

CPC分类号： G06N10/40 ,  G01R33/0354

摘要： An output-amplifier-based reciprocal quantum logic (RQL) bias-level sensor is used to measure and/or calibrate bias parameters of AC and/or DC bias signals provided to RQL circuitry. The bias signals can include an output amplifier output bias current. The bias-level sensor includes a stack of DC SQUIDs that are supplied their inputs from outputs of respective Josephson transmission lines (JTLs) to which the SQUIDs are transformer-coupled. Staging relative strengths of the bias taps of the JTLs, or the critical currents of the Josephson junctions in the DC SQUIDs, allows an output voltage signal of the bias-level sensor to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range. The outputs of two such bias-level sensors driven by I and Q clocks can be compared to adjust AC bias amplitudes of the clocks. Relative clock phase can be similarly adjusted.