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公开(公告)号：US20190007037A1
公开(公告)日：2019-01-03
申请号：US15635728
申请日：2017-06-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Dacheng Zhou , Daniel Alan Berkram , Ryan Barnhill , Christopher Allan Poirier , Christopher Wilson
CPC classification number: H03K5/24 , G01D5/204 , H03F3/45479 , H03K19/20 , H03M9/00 , H04L25/0272 , H04L25/03076
Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.
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公开(公告)号：US10075150B2
公开(公告)日：2018-09-11
申请号：US15227326
申请日：2016-08-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Christopher Allan Poirier , Ryan Barnhill , Dacheng Zhou
IPC: H03K3/356
CPC classification number: H03K3/356121 , H03K3/356113
Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
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Patent Agency Ranking
公开(公告)号：US11201607B2
公开(公告)日：2021-12-14
申请号：US16121570
申请日：2018-09-04
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Christopher Allan Poirier , Ryan Barnhill , Dacheng Zhou
IPC: H03K3/356
Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
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公开(公告)号：US20180375501A1
公开(公告)日：2018-12-27
申请号：US16121570
申请日：2018-09-04
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Christopher Allan Poirier , Ryan Barnhill , Dacheng Zhou
IPC: H03K3/356
Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
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公开(公告)号：US10389342B2
公开(公告)日：2019-08-20
申请号：US15635728
申请日：2017-06-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Dacheng Zhou , Daniel Alan Berkram , Ryan Barnhill , Christopher Allan Poirier , Christopher Wilson
IPC: H03L7/08 , G06F17/10 , B62D5/04 , H03M1/48 , H03F1/02 , G01S1/00 , H03M1/64 , H03K5/24 , H03F3/45 , H03K19/20 , G01D5/20 , H03M9/00 , H04L25/03
Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.
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公开(公告)号：US10270444B1
公开(公告)日：2019-04-23
申请号：US15945471
申请日：2018-04-04
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Edward James Luckett , Christopher Allan Poirier
IPC: H03K19/003
Abstract: According to examples, an apparatus may include a field effect transistor (FET), a driver to receive an input signal and to output a driver output signal, and a gate to receive the input signal. The apparatus may also include a delay element to receive the driver output signal and to output a delayed signal to the gate after a delay from receipt of the driver output signal, in which the gate is to output a gate output signal to the FET in response to receipt of the input signal and the delayed signal, and in which receipt of the gate output signal by the FET drives the FET to provide a boost to the driver output signal.
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公开(公告)号：US20180041199A1
公开(公告)日：2018-02-08
申请号：US15227326
申请日：2016-08-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Christopher Allan Poirier , Ryan Barnhill , Dacheng Zhou
IPC: H03K3/356
CPC classification number: H03K3/356121 , H03K3/356113
Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
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