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公开(公告)号:US20190334742A1
公开(公告)日:2019-10-31
申请号:US15965760
申请日:2018-04-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Clinton Harold Parker , Zhubiao Zhu , Daniel Alan Berkram
IPC: H04L25/02 , H03K17/06 , H03K17/687
Abstract: A device, including a first current supply configured to provide a bias current to a load and a main current supply having a source terminal coupled in parallel with the load and configured to reduce a current value to the load below the bias current, is provided. The device includes a termination resistor coupled in series with the source terminal of the main current supply and configured to receive current from the source terminal of the main current supply when the source terminal of the main current supply is activated. The device also includes an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at common mode voltage when current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor.
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公开(公告)号:US20230299856A1
公开(公告)日:2023-09-21
申请号:US17694866
申请日:2022-03-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: David Ritter Thomas , Laurel Abeyta , Jason Douglas Jung , Kit MacCarthy Morton , Daniel Alan Berkram
IPC: H04B10/69
CPC classification number: H04B10/697 , H04B10/691
Abstract: Examples described herein relate to a method and a system for removing the common-mode current. The receiver includes a photodetector, a common-mode adjustment circuit, an analog front-end, an eye scan circuit, and a control unit. The photodetector generates an input photocurrent responsive to a received optical signal. The common-mode adjustment circuit generates an adjusted input current based on the input photocurrent. The analog front-end generates a differential voltage based on the adjusted input current. Based on the differential voltage, the eye scan circuit generates an eye scan information defining a first outer eye and a second outer eye in an eye diagram. The control unit tunes the common-mode adjustment circuit based on a relative height metric of a first height of the first outer eye and a second height of the second outer eye to remove a portion of the common-mode current from the input photocurrent.
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公开(公告)号:US10530481B1
公开(公告)日:2020-01-07
申请号:US16057626
申请日:2018-08-07
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Terrel Morris , Daniel Alan Berkram
Abstract: The present disclosure provides an effective solution to employ hyperscale photonics connectivity using existing server connections. The solution described in the present disclosure eliminates top-of-rack switches and facilitates a manner for servers to connect directly to middle-of-row switches. An apparatus consistent with the present disclosure includes a primary transceiver device. The primary server-end transceiver device comprising a photonics transceiver and a first electrical transmitter. The apparatus further includes a first secondary server-end transceiver device, the first secondary server-end transceiver device comprising a second electrical transmitter. In addition, a first electrical cable electrically couples the primary server-end transceiver to the first secondary server-end transceiver device. The present disclosure enables the use of an input fiber connection and a photonics transceiver to effect two sets of electrical connections on different servers.
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公开(公告)号:US10389342B2
公开(公告)日:2019-08-20
申请号:US15635728
申请日:2017-06-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Dacheng Zhou , Daniel Alan Berkram , Ryan Barnhill , Christopher Allan Poirier , Christopher Wilson
IPC: H03L7/08 , G06F17/10 , B62D5/04 , H03M1/48 , H03F1/02 , G01S1/00 , H03M1/64 , H03K5/24 , H03F3/45 , H03K19/20 , G01D5/20 , H03M9/00 , H04L25/03
Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.
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公开(公告)号:US12003279B2
公开(公告)日:2024-06-04
申请号:US17694866
申请日:2022-03-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: David Ritter Thomas , Laurel Abeyta , Jason Douglas Jung , Kit Maccarthy Morton , Daniel Alan Berkram
IPC: H04B10/69
CPC classification number: H04B10/697 , H04B10/691
Abstract: Examples described herein relate to a method and a system for removing the common-mode current. The receiver includes a photodetector, a common-mode adjustment circuit, an analog front-end, an eye scan circuit, and a control unit. The photodetector generates an input photocurrent responsive to a received optical signal. The common-mode adjustment circuit generates an adjusted input current based on the input photocurrent. The analog front-end generates a differential voltage based on the adjusted input current. Based on the differential voltage, the eye scan circuit generates an eye scan information defining a first outer eye and a second outer eye in an eye diagram. The control unit tunes the common-mode adjustment circuit based on a relative height metric of a first height of the first outer eye and a second height of the second outer eye to remove a portion of the common-mode current from the input photocurrent.
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公开(公告)号:US11114820B2
公开(公告)日:2021-09-07
申请号:US16186822
申请日:2018-11-12
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Zhubiao Zhu , Clinton Harold Parker , Daniel Alan Berkram
IPC: H01S5/042 , H01S3/13 , H01S5/183 , H04B10/508 , H05B45/32
Abstract: A push-pull circuit for an opto-electronic device includes: an output node; a pull-up circuit that, in operation, controls a falling edge rate of an input signal to the opto-electronic device while sharing charge with the output node; and a pull-down circuit that, in operation, controls a rising edge rate of the input signal to the opto-electronic device while sharing charge with the output node.
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公开(公告)号:US20190007037A1
公开(公告)日:2019-01-03
申请号:US15635728
申请日:2017-06-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Dacheng Zhou , Daniel Alan Berkram , Ryan Barnhill , Christopher Allan Poirier , Christopher Wilson
CPC classification number: H03K5/24 , G01D5/204 , H03F3/45479 , H03K19/20 , H03M9/00 , H04L25/0272 , H04L25/03076
Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.
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公开(公告)号:US10791385B2
公开(公告)日:2020-09-29
申请号:US16147481
申请日:2018-09-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Terrel Morris , John Norton , Daniel Alan Berkram
IPC: H04J14/00 , H04Q11/00 , G02B6/42 , H05K1/18 , H05K1/02 , H05K1/11 , H05K7/14 , H01R12/72 , H01R12/75
Abstract: A pluggable module is provided for converting an optical signal to a plurality of electrical signals. The pluggable module may include a printable circuit board (PCB) and an optical connector disposed on a first side of the PCB. The optical connector may route any received optical signal to an optical to electrical transceiver. The optical to electrical transceiver may convert the optical signal to an electrical signal and route the electrical signal to an electrical connector mounted on a second, opposite side of the PCB.
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公开(公告)号:US20200107087A1
公开(公告)日:2020-04-02
申请号:US16147481
申请日:2018-09-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Terrel Morris , John Norton , Daniel Alan Berkram
Abstract: A pluggable module is provided for converting an optical signal to a plurality of electrical signals. The pluggable module may include a printable circuit board (PCB) and an optical connector disposed on a first side of the PCB. The optical connector may route any received optical signal to an optical to electrical transceiver. The optical to electrical transceiver may convert the optical signal to an electrical signal and route the electrical signal to an electrical connector mounted on a second, opposite side of the PCB.
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公开(公告)号:US10484089B1
公开(公告)日:2019-11-19
申请号:US15965773
申请日:2018-04-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Zhubiao Zhu , Clinton Harold Parker , Daniel Alan Berkram
IPC: H04B10/50 , H04B10/58 , H04L25/03 , H04B10/079 , H03F1/32 , H03F1/22 , H05B41/32 , H03K3/26 , H03K7/06 , H03K3/37
Abstract: A device, including a switch configured to couple a current source with an output terminal upon receipt of a data signal, is provided. The device also includes a first variable capacitor coupled in parallel to the current source at a common node on a source terminal of the switch, wherein the first variable capacitor comprises multiple capacitive elements coupled in parallel and configured to be activated by a programmable signal, and wherein the programmable signal is selected to increase a charge transfer rate from an output terminal coupled to a load, when the switch is turned on. A system and a serial interface including the above device are also provided.
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