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    SET-RESET LATCHES
    2.
    发明申请
    SET-RESET LATCHES 审中-公开

    公开(公告)号：US20180041199A1

    公开(公告)日：2018-02-08

    申请号：US15227326

    申请日：2016-08-03

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Christopher Allan Poirier ,  Ryan Barnhill ,  Dacheng Zhou

    IPC: H03K3/356

    CPC classification number: H03K3/356121 ,  H03K3/356113

    Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

    Method and system for improving analog-to-digital conversion performance
    5.
    发明授权
    Method and system for improving analog-to-digital conversion performance 有权

    公开(公告)号：US12132492B2

    公开(公告)日：2024-10-29

    申请号：US18081490

    申请日：2022-12-14

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dacheng Zhou ,  Peter Tsugio Kurahashi ,  Ryan Barnhill ,  Michael James Marshall

    IPC: H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/38

    CPC classification number: H03M1/0607 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/167 ,  H03M1/38

    Abstract: A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.

    CLOCK SYNCHRONIZATION IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERSION
    6.
    发明公开
    CLOCK SYNCHRONIZATION IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERSION 审中-公开

    公开(公告)号：US20240255983A1

    公开(公告)日：2024-08-01

    申请号：US18161927

    申请日：2023-01-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Dacheng Zhou ,  Peter Tsugio Kurahashi

    IPC: G06F1/12 ,  G06F1/08

    CPC classification number: G06F1/12 ,  G06F1/08

    Abstract: A TI-ADC circuit and method therefor include the use of first and second level clock generators configured to receive an asynchronous reference clock signal and generate a plurality of first and second clock signals, the second level clock generator including a plurality of clock dividers connected in series, respective ones of the plurality of clock dividers being configured to divide an input clock signal in accordance with a synchronization signal; a plurality of T/H circuits respectively configured to operate in accordance with one of the first clock signals; a plurality of sub-ADCs respectively configured to operate in accordance with one of the second clock signals, thereby to sample an input signal in a time-interleaved manner, wherein for a given clock divider of the plurality of clock dividers, the synchronization signal corresponds to an output clock of a clock divider immediately upstream from the given clock divider.

    Feedback circuit for a decision feedback equalizer
    7.
    发明授权
    Feedback circuit for a decision feedback equalizer 有权

    公开(公告)号：US11196593B1

    公开(公告)日：2021-12-07

    申请号：US16943834

    申请日：2020-07-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dacheng Zhou ,  Daniel Alan Berkram ,  Ryan Barnhill

    IPC: H04L25/03 ,  H03K5/24 ,  G06F1/06 ,  H04L27/04 ,  H03K19/20

    Abstract: One embodiment can provide a sampler for a decision feedback equalizer (DFE). The sampler can include a comparator comprising a resolver and a plurality of amplifiers coupled to the resolver. The plurality of amplifiers are to receive an input signal and one or more feedback signals, and the plurality of amplifiers are coupled to each other in parallel, thereby facilitating a summation of the input signal and the one or more feedback signals. The comparator is to generate an output based on the summation of the input signals and the one or more feedback signals. The sampler can further include an inverter to invert the output of the comparator. The inverted output of the inverter is sent to a tap-1 amplifier to generate a tap-1 feedback signal to be sent to the comparator at a next unit interval (UI).

    Methods and apparatus to generate a circuit protection voltage
    8.
    发明授权
    Methods and apparatus to generate a circuit protection voltage 有权

    公开(公告)号：US10734988B2

    公开(公告)日：2020-08-04

    申请号：US15853215

    申请日：2017-12-22

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dacheng Zhou

    IPC: H03K17/00 ,  H03K17/08 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3206 ,  H03K17/042 ,  H03K17/51 ,  H03K17/56

    Abstract: Apparatus, methods and systems to produce a protection voltage are disclosed. The apparatus includes circuitry to deliver a first supply voltage to a plurality of circuits, where the first supply voltage has a first magnitude, circuitry to deliver a second supply voltage to a part of the plurality of circuits, where the second supply voltage has a second magnitude, and circuitry to deliver a protection voltage to the part of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH. The protection voltage has a magnitude that is a fraction of the magnitude of the first supply voltage. The apparatus includes circuitry that causes the delivery of the second supply voltage to the part of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

    Termination voltage circuits
    10.
    发明授权
    Termination voltage circuits 有权

    公开(公告)号：US10153611B2

    公开(公告)日：2018-12-11

    申请号：US15500081

    申请日：2015-04-09

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Dacheng Zhou ,  Daniel Alan Berkram ,  Zhubiao Zhu

    IPC: H01S5/042 ,  H03K19/0185 ,  H01S5/183 ,  H03K19/00

    Abstract: An example driver circuit includes a termination voltage circuit and a termination element coupled to the termination voltage circuit. The driver circuit also includes a current source switch coupled the termination element via a node. The driver circuit further includes a current source coupled to the current source switch. The current source switch and the termination voltage circuit are controlled via a control signal. The termination voltage circuit is to generate a termination voltage to match a node voltage of the node based on the control signal. The driver circuit further includes a load coupled to the termination element and the current source switch via the node. The driver circuit further includes a load voltage source coupled to the load. The node voltage is generated based on the load and the load voltage source.

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