公开(公告)号：US10389342B2

公开(公告)日：2019-08-20

申请号：US15635728

申请日：2017-06-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dacheng Zhou ,  Daniel Alan Berkram ,  Ryan Barnhill ,  Christopher Allan Poirier ,  Christopher Wilson

IPC: H03L7/08 ,  G06F17/10 ,  B62D5/04 ,  H03M1/48 ,  H03F1/02 ,  G01S1/00 ,  H03M1/64 ,  H03K5/24 ,  H03F3/45 ,  H03K19/20 ,  G01D5/20 ,  H03M9/00 ,  H04L25/03

Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

公开(公告)号：US20190007037A1

公开(公告)日：2019-01-03

申请号：US15635728

申请日：2017-06-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dacheng Zhou ,  Daniel Alan Berkram ,  Ryan Barnhill ,  Christopher Allan Poirier ,  Christopher Wilson

IPC: H03K5/24 ,  H03F3/45 ,  H03K19/20 ,  G01D5/20

CPC classification number: H03K5/24 ,  G01D5/204 ,  H03F3/45479 ,  H03K19/20 ,  H03M9/00 ,  H04L25/0272 ,  H04L25/03076

Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.