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公开(公告)号：US20190007037A1
公开(公告)日：2019-01-03
申请号：US15635728
申请日：2017-06-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Dacheng Zhou , Daniel Alan Berkram , Ryan Barnhill , Christopher Allan Poirier , Christopher Wilson
CPC classification number: H03K5/24 , G01D5/204 , H03F3/45479 , H03K19/20 , H03M9/00 , H04L25/0272 , H04L25/03076
Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.
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公开(公告)号：US20240146264A1
公开(公告)日：2024-05-02
申请号：US17976713
申请日：2022-10-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ryan Barnhill , Jacquelyn Mary Ingemi , Michael James Marshall , James S. Ignowski
IPC: H03F3/45
CPC classification number: H03F3/45475 , H03F2200/375
Abstract: One aspect can provide a direct current (DC) feedback circuit. The DC feedback circuit can include a gain path, a first feedback capacitor coupled, in parallel, to the gain path, and an input resistor coupled to an input of the gain path and the first feedback capacitor. The gain path can include an input stage with a pair of transconductance amplifiers, a gain stage with one or more amplifiers, and an output stage with at least one negative feedback amplifier.
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公开(公告)号：US10389342B2
公开(公告)日：2019-08-20
申请号：US15635728
申请日：2017-06-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Dacheng Zhou , Daniel Alan Berkram , Ryan Barnhill , Christopher Allan Poirier , Christopher Wilson
IPC: H03L7/08 , G06F17/10 , B62D5/04 , H03M1/48 , H03F1/02 , G01S1/00 , H03M1/64 , H03K5/24 , H03F3/45 , H03K19/20 , G01D5/20 , H03M9/00 , H04L25/03
Abstract: A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.
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公开(公告)号：US20180041199A1
公开(公告)日：2018-02-08
申请号：US15227326
申请日：2016-08-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Christopher Allan Poirier , Ryan Barnhill , Dacheng Zhou
IPC: H03K3/356
CPC classification number: H03K3/356121 , H03K3/356113
Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
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公开(公告)号：US20240204789A1
公开(公告)日：2024-06-20
申请号：US18081490
申请日：2022-12-14
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dacheng Zhou , Peter Tsugio Kurahashi , Ryan Barnhill , Michael James Marshall
IPC: H03M1/06
CPC classification number: H03M1/0607
Abstract: A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.
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Patent Agency Ranking
公开(公告)号：US11201607B2
公开(公告)日：2021-12-14
申请号：US16121570
申请日：2018-09-04
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Christopher Allan Poirier , Ryan Barnhill , Dacheng Zhou
IPC: H03K3/356
Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
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公开(公告)号：US20180375501A1
公开(公告)日：2018-12-27
申请号：US16121570
申请日：2018-09-04
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Christopher Allan Poirier , Ryan Barnhill , Dacheng Zhou
IPC: H03K3/356
Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
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公开(公告)号：US12132492B2
公开(公告)日：2024-10-29
申请号：US18081490
申请日：2022-12-14
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dacheng Zhou , Peter Tsugio Kurahashi , Ryan Barnhill , Michael James Marshall
CPC classification number: H03M1/0607 , H03M1/1215 , H03M1/1245 , H03M1/167 , H03M1/38
Abstract: A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.
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公开(公告)号：US11196593B1
公开(公告)日：2021-12-07
申请号：US16943834
申请日：2020-07-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dacheng Zhou , Daniel Alan Berkram , Ryan Barnhill
Abstract: One embodiment can provide a sampler for a decision feedback equalizer (DFE). The sampler can include a comparator comprising a resolver and a plurality of amplifiers coupled to the resolver. The plurality of amplifiers are to receive an input signal and one or more feedback signals, and the plurality of amplifiers are coupled to each other in parallel, thereby facilitating a summation of the input signal and the one or more feedback signals. The comparator is to generate an output based on the summation of the input signals and the one or more feedback signals. The sampler can further include an inverter to invert the output of the comparator. The inverted output of the inverter is sent to a tap-1 amplifier to generate a tap-1 feedback signal to be sent to the comparator at a next unit interval (UI).
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公开(公告)号：US10075150B2
公开(公告)日：2018-09-11
申请号：US15227326
申请日：2016-08-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Christopher Allan Poirier , Ryan Barnhill , Dacheng Zhou
IPC: H03K3/356
CPC classification number: H03K3/356121 , H03K3/356113
Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
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