-
公开(公告)号：US09972387B2
公开(公告)日：2018-05-15
申请号：US15325040
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Martin Foltin , Yoocharn Jeon , Brent Buchanan , Erik Ordentlich , Naveen Muralimanohar , James S. Ignowski , Jacquelyn M. Ingemi
CPC classification number: G11C13/004 , G11C7/06 , G11C13/0038 , G11C13/0059 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2207/068
Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.
-
公开(公告)号：US20170213590A1
公开(公告)日：2017-07-27
申请号：US15324792
申请日：2014-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Erik Ordentlich
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0002 , G11C13/0007 , G11C27/02 , G11C2013/0042 , G11C2013/0045 , G11C2013/0057
Abstract: According to an example, in a method for determining a resistance state of a cell in a crossbar memory array, a first read voltage may be applied across a cell to sense a first cell current. In addition, a second read voltage may be applied across the cell to sense a second cell current. A difference value between the first cell current and the second cell current may be identified and a resistance state of the cell may be determined based on the difference value.
-
公开(公告)号：US20160352358A1
公开(公告)日：2016-12-01
申请号：US15112013
申请日：2014-01-24
Applicant: HEWLETT-PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Erik Ordentlich , Ron M. Roth
CPC classification number: H03M13/1575 , G06F11/1068 , G11C29/52 , H03M13/2921 , H03M13/47 , H03M13/51
Abstract: Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range Δ of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.
Abstract translation: 位翻转编码使用位触发编码器翻转具有n行和n列的二进制数组的冗余相交向量中的位，直到二进制数组的汉明权重在n的预定范围Δ除以2。 位数翻转编码装置的输入数据字的信息位被存储在二进制数组内不被冗余向量的n个冗余比特占用的位置中。
-
公开(公告)号：US20160343431A1
公开(公告)日：2016-11-24
申请号：US15113908
申请日：2014-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B. Lesartre , Gary Gibson , Erik Ordentlich , Yoocham Jeon
IPC: G11C13/00
CPC classification number: G11C13/003 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/77 , H01L27/2463
Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.
Abstract translation: 一种设备包括交叉点阵列和访问电路，以访问分别对应于编码的数据块的存储器元件的子集。 对于存储器元件的每个子集，包括子集中的第一存储器元件和该子集中的第二存储器元件的交叉点阵列的行或列还包括位于第一和第二存储器元件之间的第三存储器元件 沿着行或列的存储器元件，并且在对应于另一编码块的子集之一中。
-
公开(公告)号：US10175906B2
公开(公告)日：2019-01-08
申请号：US15325118
申请日：2014-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Erik Ordentlich , Cong Xu
Abstract: In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.
-
Patent Agency Ranking
公开(公告)号：US10146619B2
公开(公告)日：2018-12-04
申请号：US15320852
申请日：2014-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Erik Ordentlich , Amit S. Sharma
Abstract: According to an example, a method for assigning redundancy in encoding data onto crossbar memory arrays is provided wherein each of said crossbar memory arrays include cells. The data may be allocated to a subset of the cells in multiple crossbar memory arrays. The redundancy for the data may then be assigned based on coordinates of the subset of cells within the multiple crossbar memory arrays onto which the data is allocated.
-
公开(公告)号：US09721656B2
公开(公告)日：2017-08-01
申请号：US15113908
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Gregg B. Lesartre , Gary Gibson , Erik Ordentlich , Yoocharn Jeon
CPC classification number: G11C13/003 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/77 , H01L27/2463
Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.
-
公开(公告)号：US20170192711A1
公开(公告)日：2017-07-06
申请号：US15325118
申请日：2014-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Erik Ordentlich , Cong Xu
IPC: G06F3/06
CPC classification number: G06F3/0638 , G06F3/0604 , G06F3/0679 , G11C7/1012 , G11C13/0069 , G11C2213/77
Abstract: In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.
-
公开(公告)号：US10320420B2
公开(公告)日：2019-06-11
申请号：US15112013
申请日：2014-01-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Erik Ordentlich , Ron M. Roth
Abstract: Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range Δ of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.
-
公开(公告)号：US09952796B2
公开(公告)日：2018-04-24
申请号：US15113890
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Erik Ordentlich , Ron M. Roth
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0644 , G06F3/0679 , G06F11/1068 , G06F12/0238 , G06F12/0607 , G11C29/52 , G11C2029/0411
Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, input bits are encoded into an intermediate binary array having multiple sub-arrays iteratively appended row-wise to the intermediate binary array. First sub-array is generated based on the input bits such that each row of the first sub-array has a number of 1's equal to a fraction of number of columns in the first sub-array, and based on a column balance coding such that the columns of the first sub-array have an equal number of 1's. At least one subsequent sub-array is generated based on a set of bits obtained from balancing termination indices for a previous sub-array and from diagonal bits of the intermediate binary array that are a part of the previous appended sub-array. The intermediate binary array is transformed to an encoded bit pattern. The encoded bit pattern is stored in the memory array.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.018 seconds)
