公开(公告)号：US20240146264A1

公开(公告)日：2024-05-02

申请号：US17976713

申请日：2022-10-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ryan Barnhill ,  Jacquelyn Mary Ingemi ,  Michael James Marshall ,  James S. Ignowski

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F2200/375

Abstract: One aspect can provide a direct current (DC) feedback circuit. The DC feedback circuit can include a gain path, a first feedback capacitor coupled, in parallel, to the gain path, and an input resistor coupled to an input of the gain path and the first feedback capacitor. The gain path can include an input stage with a pair of transconductance amplifiers, a gain stage with one or more amplifiers, and an output stage with at least one negative feedback amplifier.

公开(公告)号：US09972387B2

公开(公告)日：2018-05-15

申请号：US15325040

申请日：2014-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Martin Foltin ,  Yoocharn Jeon ,  Brent Buchanan ,  Erik Ordentlich ,  Naveen Muralimanohar ,  James S. Ignowski ,  Jacquelyn M. Ingemi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C13/0038 ,  G11C13/0059 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2207/068

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

公开(公告)号：US20170206956A1

公开(公告)日：2017-07-20

申请号：US15325040

申请日：2014-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Martin Foltin ,  Yoocharn Jeon ,  Brent Buchanan ,  Erik Ordentlich ,  Naveen Muralimanohar ,  James S. Ignowski ,  Jacquelyn M. Ingemi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C13/0038 ,  G11C13/0059 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2207/068

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

公开(公告)号：US20250077181A1

公开(公告)日：2025-03-06

申请号：US18460322

申请日：2023-09-01

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Giacomo Pedretti ,  James S. Ignowski

IPC: G06F7/544 ,  G06F7/523 ,  H03M1/12 ,  H03M1/66

Abstract: A computing system that includes an attention engine is disclosed. The attention engine is an in-memory computing module that may be used to accelerate attention operations. The attention engine includes a dot product circuit and a multiplier circuit, which together are used to perform matrix generation and matrix multiplication in the analog domain. Performing matrix multiplication in the analog domain may be faster and/or consume less power than performing matrix multiplication in the digital domain.

公开(公告)号：US09934854B2

公开(公告)日：2018-04-03

申请号：US15500074

申请日：2014-11-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Yoocharn Jeon ,  James S. Ignowski

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G06F13/1668 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

Abstract: A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to determine a first measured voltage that drives a first read current through a selected memory cell of the crossbar array. The voltage driver applies the variable voltage to the selected line to determine a second measured voltage that drives a second read current through the selected memory cell. The voltage comparator then determines a voltage difference between the first measured voltage and the second measured voltage and to compare the voltage difference with a reference voltage difference to determine a state of the selected memory cell. The crossbar array comprises a plurality of row lines, a plurality of column lines, and a plurality of memory cells. Each memory cell is coupled between a unique combination of one row line and one column line.