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    Memory cell that prevents charge loss
    1.
    发明授权
    Memory cell that prevents charge loss 有权
    防止电荷损失的存储单元

    公开(公告)号：US09559106B2

    公开(公告)日：2017-01-31

    申请号：US14397571

    申请日：2012-10-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Chaw-Sing Ho ,  Reynaldo Villavelez ,  Xin Ping Cao

    IPC: H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

    CPC classification number: H01L27/11521 ,  B41J2/1433 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788 ,  H01L29/7881

    Abstract: A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer.

    Abstract translation: 一种存储单元，包括基板，第一介电层，浮栅，第二介质层和控制栅。 衬底包括位于漏极区域和源极区域之间的沟道区域。 第一电介质层位于沟道区上方，并且浮栅通过第一介电层电容耦合到沟道区。 第二介电层位于浮动栅极之上，并且控制栅极通过第二介电层电容耦合到浮置栅极。 电介质氮化物层位于浮置栅极和第二介电层之间，以防止从浮置栅极到第二介电层的电荷损失。

    Fluid ejection devices comprising memory cells
    3.
    发明授权
    Fluid ejection devices comprising memory cells 有权

    公开(公告)号：US10319728B2

    公开(公告)日：2019-06-11

    申请号：US15379286

    申请日：2016-12-14

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Chaw Sing Ho ,  Reynaldo V. Villavelez ,  Xin Ping Cao

    IPC: H01L27/11524 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  B41J2/14 ,  H01L21/28 ,  H01L29/51

    Abstract: In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.

    MEMORY CELL THAT PREVENTS CHARGE LOSS
    4.
    发明申请
    MEMORY CELL THAT PREVENTS CHARGE LOSS 有权
    存储器电池，防止充电损失

    公开(公告)号：US20150123186A1

    公开(公告)日：2015-05-07

    申请号：US14397571

    申请日：2012-10-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Chaw-Sing Ho ,  Reynaldo Villavelez ,  Xin Ping Cao

    IPC: H01L29/788 ,  H01L27/115 ,  H01L21/28

    CPC classification number: H01L27/11521 ,  B41J2/1433 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788 ,  H01L29/7881

    Abstract: A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer.

    Abstract translation: 一种存储单元，包括基板，第一介电层，浮栅，第二介质层和控制栅。 衬底包括位于漏极区域和源极区域之间的沟道区域。 第一电介质层位于沟道区上方，并且浮栅通过第一介电层电容耦合到沟道区。 第二介电层位于浮动栅极之上，并且控制栅极通过第二介电层电容耦合到浮置栅极。 电介质氮化物层位于浮置栅极和第二介电层之间，以防止从浮置栅极到第二介电层的电荷损失。

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