公开(公告)号：US20220376109A1

公开(公告)日：2022-11-24

申请号：US17642811

申请日：2020-06-18

Applicant: Hitachi, Ltd. ,  TOYO TANSO CO., LTD

Inventor： Keisuke Kobayashi ,  Kumiko Konishi ,  Akio Shima ,  Norihito Yabuki ,  Yusuke Sudoh ,  Satoru Nogami ,  Makoto Kitabatake

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L21/04

Abstract: To provide a technique capable of improving performance and reliability of a semiconductor device. An n−-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p+-type body region (14), n+-type current spreading regions (16, 17), and a trench. TR are formed in the n−-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p+-type body region (14), a side surface S1 of the trench TR is in contact with the n+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n−-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench. Furthermore, an angle θ1 at which the upper surface T1 of the n−-type epitaxial layer (12) is inclined with respect to the side surface S1 is smaller than an angle θ2 at which the upper surface T1 of the n−-type epitaxial layer (12) is inclined with respect to the side surface S2.

公开(公告)号：US10062759B2

公开(公告)日：2018-08-28

申请号：US14778058

申请日：2013-03-29

Applicant: HITACHI, LTD.

Inventor： Digh Hisamoto ,  Keisuke Kobayashi ,  Naoki Tega ,  Toshiyuki Ohno ,  Hirotaka Hamamura ,  Mieko Matsumura

IPC: H01L29/15 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/045 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1033 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/872

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

公开(公告)号：US10229974B2

公开(公告)日：2019-03-12

申请号：US15560428

申请日：2015-05-18

Applicant: HITACHI, LTD.

Inventor： Mieko Matsumura ,  Junichi Sakano ,  Naoki Tega ,  Yuki Mori ,  Haruka Shimizu ,  Keisuke Kobayashi

IPC: H01L29/16 ,  H01L29/73 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

公开(公告)号：US10032871B2

公开(公告)日：2018-07-24

申请号：US14778058

申请日：2013-03-29

Applicant: HITACHI, LTD.

Inventor： Digh Hisamoto ,  Keisuke Kobayashi ,  Naoki Tega ,  Toshiyuki Ohno ,  Hirotaka Hamamura ,  Mieko Matsumura

IPC: H01L29/15 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

公开(公告)号：US09490328B2

公开(公告)日：2016-11-08

申请号：US14897247

申请日：2013-06-06

Applicant: HITACHI, LTD.

Inventor： Naoki Tega ,  Keisuke Kobayashi ,  Koji Fujisaki ,  Takashi Takahama

IPC: H01L29/15 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L29/10 ,  H01L29/167

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0465 ,  H01L21/0485 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7811

Abstract: In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.

Abstract translation: 为了提供高性能和可靠的碳化硅半导体器件，在包括n型SiC外延衬底，p型体层，p型体层电位固定区和氮化硅电极固定区的碳化硅半导体器件中， 引入形成在p型体层中的n型第一源极区域，在氮 - 氮化物区域内形成n型第二源区，其中具有高于氮的固溶度极限的磷并容易扩散的磷， 引入n型第一源极区域以与p型体层电位固定区域和p型体层电位固定区域分离。