公开(公告)号：US09570601B2

公开(公告)日：2017-02-14

申请号：US14904685

申请日：2013-07-16

Applicant: HITACHI, LTD.

Inventor： Yuki Mori ,  Toshiyuki Mine ,  Hiroshi Miki ,  Mieko Matsumura ,  Hirotaka Hamamura

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L29/7802 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66068

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract translation: 提供了一种在半导体器件中与Si功率MOSFET一样多地确保栅极绝缘膜的可靠性的技术，其中使用具有比硅更大的带隙的半导体材料，并且其典型例如为 一个SiC功率MOSFET。 为了实现该目的，在SiC功率MOSFET中，栅电极GE形成为与栅极绝缘膜GOX接触，并且由厚度等于或小于200nm的多晶硅膜PF1形成， 和形成为与多晶硅膜PF1接触并且具有任何厚度的多晶硅膜PF2。

公开(公告)号：US10062759B2

公开(公告)日：2018-08-28

申请号：US14778058

申请日：2013-03-29

Applicant: HITACHI, LTD.

Inventor： Digh Hisamoto ,  Keisuke Kobayashi ,  Naoki Tega ,  Toshiyuki Ohno ,  Hirotaka Hamamura ,  Mieko Matsumura

IPC: H01L29/15 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/045 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1033 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/872

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

公开(公告)号：US20140217422A1

公开(公告)日：2014-08-07

申请号：US14240376

申请日：2012-03-30

Applicant: HITACHI, LTD.

Inventor： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

IPC: H01L29/16 ,  H01L29/792

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/049 ,  H01L29/513 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/792

Abstract: In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage.

Abstract translation: 在使用SiC衬底的SiC-MOSFET功率器件中，采用具有电荷俘获特性的层叠绝缘膜作为SiC-DiMOSFET的栅极绝缘膜，并且将电荷注入到层叠绝缘膜中，从而抑制 门极电压的变化。

公开(公告)号：US09508611B2

公开(公告)日：2016-11-29

申请号：US14911651

申请日：2013-08-14

Applicant: HITACHI, LTD.

Inventor： Yoshinobu Kimura ,  Natsuki Tsuno ,  Hiroya Ohta ,  Renichi Yamada ,  Hirotaka Hamamura ,  Toshiyuki Ohno ,  Hiroyuki Okino ,  Yuki Mori

IPC: H01L21/66 ,  G01R31/265

CPC classification number: H01L22/12 ,  G01R31/265 ,  H01L22/20 ,  H01L22/24

Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.

Abstract translation: 在使用半导体检查装置的半导体检查方法中，通过选择入射能量和负电位并扫描具有一次电子的晶片的检查表面以检测二次电子，获得第一检查图像，并且存在宏观缺陷，堆垛层错 通过基于预先确定的二次电子的信号量的阈值的图像处理来判别包含在第一检查图像中的基底位错和穿透位错。 此外，通过选择入射能量和正电位并用一次电子扫描晶片的检查表面以检测二次电子，获得第二检查图像，并且包含在第二电极中的点状图形的螺纹螺钉脱位 基于预先确定的二次电子的信号量的阈值的图像处理来判别检查图像。

公开(公告)号：US10032871B2

公开(公告)日：2018-07-24

申请号：US14778058

申请日：2013-03-29

Applicant: HITACHI, LTD.

Inventor： Digh Hisamoto ,  Keisuke Kobayashi ,  Naoki Tega ,  Toshiyuki Ohno ,  Hirotaka Hamamura ,  Mieko Matsumura

IPC: H01L29/15 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

公开(公告)号：US20130341711A1

公开(公告)日：2013-12-26

申请号：US13921398

申请日：2013-06-19

Applicant: Hitachi, Ltd.

Inventor： Daisuke Matsumoto ,  Toshiyuki Ohno ,  Hirotaka Hamamura

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7828

Abstract: A technique for improving the characteristics of a semiconductor device (UMOSFET) is provided. In the UMOSFET in order to grow an epitaxial growth film on a trench side wall with an even film thickness, a channel is arranged in an optimum direction as a growth surface. For example, a trench is formed on an SiC substrate having a {0001} surface 4° off in a direction as a main surface so that a channel surface becomes a {1-100} surface. With this configuration, an epitaxial growth with the even thickness can be conducted on the side wall from which the {1-100} surface of the trench is exposed. As a result, the unevenness of a channel resistance, and the insulation failure of a gate insulating film do not occur, and the yield is improved.

Abstract translation: 提供了一种用于改善半导体器件（UMOSFET）的特性的技术。 在UMOSFET中，为了在具有均匀膜厚度的沟槽侧壁上生长外延生长膜，将通道作为生长表面以最佳方向布置。 例如，在具有{0001}表面在[11-20]方向上以{11-20}方向离开的SiC衬底上形成沟槽作为主表面，使得沟道表面变为{1-100}表面。 利用这种构造，可以在沟槽的{1-100}表面暴露的侧壁上进行具有均匀厚度的外延生长。 结果，不会发生沟道电阻的不均匀性和栅极绝缘膜的绝缘破坏，并且产率提高。