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公开(公告)号：US20190392298A1
公开(公告)日：2019-12-26
申请号：US16411269
申请日：2019-05-14
Applicant: HITACHI, LTD.
Inventor： Takashi OSHIMA , Atsutake KOSUGE , Taizo YAMAWAKI
Abstract: A neural network circuit having a plurality of analog-to-digital multipliers generates an analog product-sum voltage corresponding to the sum of charge signals of each of the analog-to-digital multipliers.
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公开(公告)号：US20190199366A1
公开(公告)日：2019-06-27
申请号：US16225790
申请日：2018-12-19
Applicant: HITACHI, LTD.
Inventor： Yohei NAKAMURA , Taizo YAMAWAKI
Abstract: Provided is a sensor terminal including a sensor element, the sensor terminal further including: an ADC that converts an analog signal output from a sensor element into a digital signal; a storage device in which a plurality of first storage setting numbers being information for controlling the ADC and a plurality of pieces of first characteristic information including description of operation of the ADC are stored in association with each other; and a communication device that receives a first reception setting number from the outside of the sensor terminal, and transmits the first characteristic information corresponding to the first storage setting number that coincides with the first reception setting number, to the outside of the sensor terminal.
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公开(公告)号：US20190074845A1
公开(公告)日：2019-03-07
申请号：US15924945
申请日：2018-03-19
Applicant: Hitachi, Ltd.
Inventor： Yohei NAKAMURA , Taizo YAMAWAKI
Abstract: The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.
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4.发明申请公开(公告)号：US20140232578A1
公开(公告)日：2014-08-21
申请号：US14265762
申请日：2014-04-30
Applicant: HITACHI, LTD.
Inventor： Takashi OSHIMA , Taizo YAMAWAKI , Tomomi TAKAHASHI
IPC: H03M1/10
CPC classification number: H03M1/1009 , H03M1/00 , H03M1/0695 , H03M1/1028 , H03M1/12 , H03M1/1215 , H03M1/804
Abstract: A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.
Abstract translation: 参考A / D转换单元并联连接到时间交织的A / D转换器的公共端作为校准对象，并且构成时间交织的A / D转换单元的每个单位A / D转换单元的输出， D转换器通过使用从参考A / D转换单元输出的低速高分辨率A / D转换结果在数字区域进行校准。 另外，fCLK / N（fCLK表示时间交织的A / D转换器的总体采样率，N是并行连接的单位A / D转换单元的数量的N相对于M）被设定为操作时钟频率 参考A / D转换单元。 所有单位A / D转换单元的采样可以与参考A / D转换单元的采样顺序同步，并且参考A / D转换器的工作时钟频率可以比总的采样率慢 时间交织的A / D转换器。
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