公开(公告)号：US20170317062A1

公开(公告)日：2017-11-02

申请号：US15423611

申请日：2017-02-03

申请人： HONGBIN SHI ,  JUNHO LEE

发明人： HONGBIN SHI ,  JUNHO LEE

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/81143 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082

摘要： A method of fabricating a semiconductor package includes providing a lower semiconductor package including a lower package substrate, and a lower dummy ball and a lower solder ball on a top surface of the lower package substrate, providing an upper semiconductor package including an upper package substrate, and an upper dummy ball and an upper solder ball on a bottom surface of the upper package substrate, joining the upper dummy ball to the lower dummy ball at a first temperature to form a solder joint, and joining the upper solder ball to the lower solder ball at a second temperature to form a connection terminal.

公开(公告)号：US20170294413A1

公开(公告)日：2017-10-12

申请号：US15418077

申请日：2017-01-27

申请人： HONGBIN SHI ,  JUNHO LEE

发明人： HONGBIN SHI ,  JUNHO LEE

IPC分类号： H01L25/065 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/3178 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor package includes a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a lower mold layer disposed on the lower package substrate, and an upper package disposed on the lower package. The upper package includes an upper package substrate and an upper semiconductor chip disposed on the upper package substrate. The semiconductor package additionally includes connection terminals disposed between the lower and upper package substrates. The connection terminals comprise outermost connection terminals and inner connection terminals. The inner connection terminals are disposed between the lower semiconductor chip and outermost connection terminals. The semiconductor package further includes a first under-fill layer disposed between the lower package substrate and the upper package substrate. At least one of the outermost connection terminals is disposed outside of the lower mold layer.