III-Nitride insulating-gate transistors with passivation
    1.
    发明授权
    III-Nitride insulating-gate transistors with passivation 有权
    具有钝化的III型氮化物绝缘栅晶体管

    公开(公告)号:US09337332B2

    公开(公告)日:2016-05-10

    申请号:US14290029

    申请日:2014-05-29

    摘要: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.

    摘要翻译: 场效应晶体管(FET)包括多个半导体层,与该半导体层中的一个接触的源电极和漏电极,在源极和漏极之间的顶部半导体表面的一部分上的第一介电层,第一 沟槽延伸穿过第一介电层并具有位于顶表面或其中一个半导体层内的底部,衬在第一沟槽上并覆盖第一介电层的一部分的第二电介质层,半导体层上的第三电介质层 第一介电层和第二介电层,延伸穿过第三介电层并且具有位于第二介电层上的第一沟槽中并在第二电介质的一部分上延伸的底部的第二沟槽,以及栅电极填充 第二条沟。

    III-NITRIDE INSULATING-GATE TRANSISTORS WITH PASSIVATION
    2.
    发明申请
    III-NITRIDE INSULATING-GATE TRANSISTORS WITH PASSIVATION 有权
    具有钝化的III型氮化物绝缘栅晶体管

    公开(公告)号:US20150349117A1

    公开(公告)日:2015-12-03

    申请号:US14290029

    申请日:2014-05-29

    IPC分类号: H01L29/78 H01L29/66 H01L29/20

    摘要: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.

    摘要翻译: 场效应晶体管(FET)包括多个半导体层,与该半导体层中的一个接触的源电极和漏电极,在源极和漏极之间的顶部半导体表面的一部分上的第一介电层,第一 沟槽延伸穿过第一介电层并具有位于顶表面或其中一个半导体层内的底部,衬在第一沟槽上并覆盖第一介电层的一部分的第二电介质层,半导体层上的第三电介质层 第一介电层和第二介电层,延伸穿过第三介电层并且具有位于第二介电层上的第一沟槽中并在第二电介质的一部分上延伸的底部的第二沟槽,以及栅电极填充 第二条沟。

    Quantum dots (QD) for semiconductor integrated circuit
    3.
    发明授权
    Quantum dots (QD) for semiconductor integrated circuit 有权
    半导体集成电路的量子点(QD)

    公开(公告)号:US09117763B1

    公开(公告)日:2015-08-25

    申请号:US14028197

    申请日:2013-09-16

    IPC分类号: G06F17/50 H01L21/308

    摘要: Semiconductor device identification using quantum dot technology. A semiconductor nanocrystal based target is fabricated. A guard ring superjacent the fluorescing surface of the nanocrystal surface is provided to ensure repeatability of spectral mapping and analysis data. A transparent cap on the target may enhance performance. A system for coding a semiconductor device is described. A method is described for fabricating quantum dot targets in a methodology compatible with subsequent semiconductor fabrication process steps.

    摘要翻译: 使用量子点技术的半导体器件识别。 制造了基于半导体纳米晶体的靶。 提供了超过纳米晶体表面的荧光表面的保护环,以确保光谱映射和分析数据的重复性。 目标上的透明盖可以提高性能。 对半导体装置的编码方式进行说明。 描述了在与随后的半导体制造工艺步骤相容的方法中制造量子点靶的方法。