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公开(公告)号：US11361965B1
公开(公告)日：2022-06-14
申请号：US17074486
申请日：2020-10-19
发明人： Danny M. Kim , Rongming Chu , Yu Cao , Thaddeus D. Ladd
摘要： Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.
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公开(公告)号：US10937650B1
公开(公告)日：2021-03-02
申请号：US16676341
申请日：2019-11-06
发明人： Danny M. Kim , Rongming Chu , Yu Cao , Thaddeus D. Ladd
摘要： Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.
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公开(公告)号：US09812532B1
公开(公告)日：2017-11-07
申请号：US14838958
申请日：2015-08-28
发明人： Rongming Chu , Yu Cao , Mary Y. Chen , Zijian “Ray” Li
IPC分类号： H01L29/15 , H01L29/20 , H01L29/66 , H01L29/78 , H01L29/207
CPC分类号： H01L29/2003 , H01L29/0847 , H01L29/4236 , H01L29/513 , H01L29/66666 , H01L29/7781 , H01L29/7827
摘要： A field effect transistor includes a III-Nitride channel layer, a III-Nitride doped cap layer on the channel layer, a source electrode in contact with the III-Nitride cap layer, a drain electrode in contact with the III-Nitride cap layer, a gate electrode located between the source and the drain electrodes, and a gate dielectric layer between the gate electrode and the III-Nitride undoped channel layer, wherein the cap layer is doped to provide mobile holes, and wherein the gate dielectric layer comprises a layer of AlN in contact with the channel layer.
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公开(公告)号：US10651306B2
公开(公告)日：2020-05-12
申请号：US15687369
申请日：2017-08-25
发明人： Rongming Chu , Yu Cao
IPC分类号： H01L29/778 , H01L29/15 , H01L29/205 , H01L29/66 , H01L29/20 , H01L29/207 , H01L29/423
摘要： A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
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公开(公告)号：US10283358B2
公开(公告)日：2019-05-07
申请号：US15980554
申请日：2018-05-15
发明人： Rongming Chu , Yu Cao
摘要： Lateral PN junctions and diodes and transistors comprising lateral PN junctions and methods used in making such devices are disclosed. A method of fabricating a lateral PN junction, can comprise: conformally growing p−GaN material on a n−GaN vertical surface extending vertically from an n−GaN horizontal surface on an n−GaN drift layer to form a first PN junction, wherein the n−GaN horizontal surface extends horizontally from the n−GaN vertical surface and the n−GaN horizontal surface has a layer of dielectric material formed on the n−GaN horizontal surface that extends from the p−GaN surface.
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公开(公告)号：US20190067464A1
公开(公告)日：2019-02-28
申请号：US15687369
申请日：2017-08-25
发明人： Rongming CHU , Yu Cao
IPC分类号： H01L29/778 , H01L29/15 , H01L29/20 , H01L29/205 , H01L29/207 , H01L29/66
摘要： A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
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公开(公告)号：US09899482B2
公开(公告)日：2018-02-20
申请号：US15093710
申请日：2016-04-07
发明人： Rongming Chu , Yu Cao , Zijian Li , Adam J. Williams
IPC分类号： H01L29/15 , H01L29/205 , H01L29/872 , H01L29/66 , H01L29/20 , H01L29/06
CPC分类号： H01L29/205 , H01L29/0619 , H01L29/2003 , H01L29/66212 , H01L29/872
摘要： A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.
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公开(公告)号：US10943998B2
公开(公告)日：2021-03-09
申请号：US16829865
申请日：2020-03-25
发明人： Rongming Chu , Yu Cao
IPC分类号： H01L29/778 , H01L29/15 , H01L29/205 , H01L29/66 , H01L29/20 , H01L29/207 , H01L29/423
摘要： A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
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公开(公告)号：US10903333B2
公开(公告)日：2021-01-26
申请号：US15663584
申请日：2017-07-28
发明人： Yu Cao , Rongming Chu , Zijian Ray Li
IPC分类号： H01L29/51 , H01L29/20 , H01L29/778 , H01L29/78 , H01L29/417 , H01L29/43 , H01L29/06 , H01L21/28 , H01L29/423
摘要： A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.
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公开(公告)号：US10535518B1
公开(公告)日：2020-01-14
申请号：US15936255
申请日：2018-03-26
发明人： Danny M. Kim , Rongming Chu , Yu Cao , Thaddeus D. Ladd
摘要： Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.
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