High-Speed Serial Interface and Data Transmission Method

    公开(公告)号:US20240356670A1

    公开(公告)日:2024-10-24

    申请号:US18760627

    申请日:2024-07-01

    Inventor: Er Nie

    CPC classification number: H04L1/004 G06F2213/0008

    Abstract: A high-speed serial interface includes a physical layer circuit at a transmit end, a monitor, a clock gating circuit, a control bitstream generation circuit, and a random bitstream generation circuit. The monitor is configured to: when no service data is being sent, instruct the clock gating circuit to stop sending a clock signal to partial modules in the physical layer circuit at the transmit end. The control bitstream generation circuit sends a first control bitstream through a serializer/deserializer (SerDes), to indicate that the transmit end has turned off partial modules in the physical layer (PHY) circuit at the transmit end and so on. The random bitstream generation circuit sends a random bitstream.

    RETIMER PATH CONTROL METHOD, APPARATUS, AND SYSTEM

    公开(公告)号:US20240378170A1

    公开(公告)日:2024-11-14

    申请号:US18783056

    申请日:2024-07-24

    Inventor: Er Nie

    Abstract: This application provides a retimer path control method, apparatus, and system for wired serial data transmission. The method includes: receiving a first bitstream, where the first bitstream includes a first field, the first field includes capability information of a retimer, and the capability information indicates whether the retimer supports a low latency path; and sending a second bitstream to the retimer, where the second bitstream includes a second field, the second field includes first enter control information, the first enter control information indicates whether the retimer enters the low latency path, and the low latency path is a path with lowest latency in data transmission paths of the retimer. In this application, the path of the retimer can be effectively controlled.

    Fast equalization method, chip, and communications system

    公开(公告)号:US11496340B2

    公开(公告)日:2022-11-08

    申请号:US17100033

    申请日:2020-11-20

    Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

    Spread Spectrum Control Method and Apparatus

    公开(公告)号:US20240356579A1

    公开(公告)日:2024-10-24

    申请号:US18760636

    申请日:2024-07-01

    Inventor: Er Nie

    CPC classification number: H04B1/707 H04L7/027

    Abstract: A first apparatus receives a first training sequences block (TSB) sent by a second apparatus, where the first TSB includes second spread spectrum capability information of the second apparatus. The first apparatus determines, based on first spread spectrum capability information of the first apparatus and the second spread spectrum capability information, whether to enable spectrum spreading of the second apparatus. The first apparatus sends a second TSB to the second apparatus, where the second TSB includes first indication information, and the first indication information indicates the second apparatus to enable or not to enable the spectrum spreading.

    Transmitter Equalization Parameter Evaluation Method and Apparatus

    公开(公告)号:US20240214245A1

    公开(公告)日:2024-06-27

    申请号:US18599570

    申请日:2024-03-08

    CPC classification number: H04L25/03 H04L25/03006 H04L2025/03777

    Abstract: A transmitter equalization parameter evaluation method and an apparatus are provided. The method provided in this application is used for evaluating a transmitter equalization parameter of a high-speed interface in a first device, and the method is performed by a second device connected to the first device over a communication link. The second device first detects a status of the communication link between the first device and the second device, where the communication link is constructed through the high-speed interface in the first device. When determining that the communication link is idle, the second device performs a transmitter equalization parameter evaluation process of the high-speed interface in the first device based on the communication link. When the communication link is idle, the transmitter equalization parameter evaluation process of the high-speed interface in the first device is started. This ensures efficiency of transmitter equalization parameter evaluation.

    Fast equalization method, chip, and communications system

    公开(公告)号:US11799697B2

    公开(公告)日:2023-10-24

    申请号:US17959490

    申请日:2022-10-04

    CPC classification number: H04L25/03012 G06F13/4282 H04B1/38 G06F2213/0026

    Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

    Spread spectrum clock negotiation method, and peripheral component interconnect express device and system

    公开(公告)号:US12117955B2

    公开(公告)日:2024-10-15

    申请号:US17951473

    申请日:2022-09-23

    Inventor: Er Nie Kun Wang Pan Li

    CPC classification number: G06F13/423 G06F13/405

    Abstract: This application provides a spread spectrum clock negotiation method, and a peripheral component interconnect express device and system, to implement dynamic negotiation between a transmit end and a receive end on an SSC capability in the peripheral component interconnect express system. The method includes: A second PCIe device generates first indication information, where the first indication information is used to indicate whether the second PCIe device has a spread spectrum clock capability. The second PCIe device sends the first indication information to a first PCIe device. The first PCIe device determines, based on the first indication information, whether to perform spread spectrum clock on a reference clock of the first PCIe device.

    DATA PROCESSING METHOD AND DEVICE, AND DATA TRANSMISSION SYSTEM

    公开(公告)号:US20230418704A1

    公开(公告)日:2023-12-28

    申请号:US18462497

    申请日:2023-09-07

    CPC classification number: G06F11/10

    Abstract: This application provides a data processing method, a device, and a data transmission system. The method includes: A first device determines a first mode from a plurality of error detection and correction modes based on an obtained first status parameter of a data link. Then, the first device may indicate a second device to use the first mode for encoding, the first device may use the first mode for decoding, thereby implementing error detection and correction of transmitted data. In the method provided in this embodiment of this application, the first device and the second device may support a plurality of error detection and correction modes, and the first device may determine a used error detection and correction mode based on a status parameter of the data link.

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