公开(公告)号：US12116279B2

公开(公告)日：2024-10-15

申请号：US17723595

申请日：2022-04-19

Applicant: NORTHWESTERN UNIVERSITY

Inventor： Mark C. Hersam ,  Qiucheng Li ,  Xiaolong Liu ,  Eden B Aklile

IPC: C01B32/182 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/184 ,  C01B35/02 ,  H01L21/02 ,  H01L21/285

CPC classification number: C01B32/182 ,  C01B35/023 ,  H01L21/02425 ,  H01L21/02491 ,  H01L21/02499 ,  H01L21/02516 ,  H01L21/02527 ,  H01L21/02603 ,  H01L21/02617 ,  H01L21/28506 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/184 ,  C01B2204/06 ,  C01B2204/20

Abstract: This invention in one aspect relates to a method of synthesizing a self-assembled mixed-dimensional heterostructure including 2D metallic borophene and 1D semiconducting armchair-oriented graphene nanoribbons (aGNRs). The method includes depositing boron on a substrate to grow borophene thereon at a substrate temperature in an ultrahigh vacuum (UHV) chamber; sequentially depositing 4,4″-dibromo-p-terphenyl on the borophene grown substrate at room temperature in the UHV chamber to form a composite structure; and controlling multi-step on-surface coupling reactions of the composite structure to self-assemble a borophene/graphene nanoribbon mixed-dimensional heterostructure. The borophene/aGNR lateral heterointerfaces are structurally and electronically abrupt, thus demonstrating atomically well-defined metal-semiconductor heterojunctions.

公开(公告)号：US20240339320A1

公开(公告)日：2024-10-10

申请号：US18297462

申请日：2023-04-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Ming CHEN ,  Chia-Shiung TSAI ,  Chung-Yuan LI

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/02617 ,  H01L21/02389 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/0254 ,  H01L29/66462 ,  H01L29/7786 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/02658 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32134 ,  H01L29/2003

Abstract: Using surface activated bonding (SAB) allows direct bonding of a silicon growth seed layer over an aluminum nitride substrate without an intervening oxide layer. The growth seed layer may include p− Si(111) in order to allow for epitaxy of gallium nitride without exacerbating CTE mismatch between silicon and the gallium nitride. As a result, defects in the gallium nitride are reduced, and bowing and cracking of the substrate is reduced, which improves performance of an electronic device including the gallium nitride. Additionally, using SAB is faster than other techniques for forming a growth seed layer as well as conserving power, processing resources, and raw materials that otherwise would have been expended in forming the growth seed layer.

公开(公告)号：US11916111B2

公开(公告)日：2024-02-27

申请号：US17969420

申请日：2022-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  iBeam Materials, Inc.

Inventor： Junhee Choi ,  Joohun Han ,  Vladimir Matias

IPC: H01L21/00 ,  H01L29/16 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L29/1604 ,  H01L21/0254 ,  H01L21/0259 ,  H01L21/02428 ,  H01L21/02488 ,  H01L21/02546 ,  H01L21/02617 ,  H01L29/04

Abstract: A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness hc.

公开(公告)号：US20180286674A1

公开(公告)日：2018-10-04

申请号：US15936751

申请日：2018-03-27

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Shishi JIANG ,  Rui CHENG ,  Abhijit Basu MALLICK

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02592 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0649

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.

公开(公告)号：US20180261461A1

公开(公告)日：2018-09-13

申请号：US15981665

申请日：2018-05-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC: H01L21/285 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/28518 ,  H01L21/02381 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L29/41783 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/7845 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate having a source feature and a drain feature therein configured to enhance charge mobility, a gate stack directly over a portion of the source feature and a portion of the drain feature, a first salicide layer over substantially the entire source feature exposed by the gate stack, and a second salicide layer over substantially the entire drain feature exposed by the gate stack. The first salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight. The second salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight.

公开(公告)号：US10032956B2

公开(公告)日：2018-07-24

申请号：US15495192

申请日：2017-04-24

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/12 ,  H01L33/32 ,  H01L33/00 ,  H01L33/10 ,  H01L33/06 ,  H01L33/24

CPC classification number: H01L33/22 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225 ,  Y02P90/265

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

公开(公告)号：US20180166533A1

公开(公告)日：2018-06-14

申请号：US15669064

申请日：2017-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ ,  Mark VAN DAL

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/465 ,  H01L29/24 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02568 ,  H01L21/02614 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02628 ,  H01L21/02639 ,  H01L21/465 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/66439 ,  H01L29/66969 ,  H01L29/785

Abstract: The present disclosure describes a method which can selectively etch silicon from silicon/silicon-germanium stacks or silicon-germanium from silicon-germanium/germanium stacks to form germanium-rich channel nanowires. For example, a method can include a multilayer stack formed with alternating layers of a silicon-rich material and a germanium-rich material. A first thin chalcogenide layer is concurrently formed on the silicon-rich material, and a second thick chalcogenide layer is formed on the germanium-rich material. The first chalcogenide layer and the second chalcogenide layer are etched until the first chalcogenide layer is removed from the silicon-rich material. The silicon-rich material and the second chalcogenide layer are etched with different etch rates.

公开(公告)号：US20180162883A1

公开(公告)日：2018-06-14

申请号：US15892839

申请日：2018-02-09

Applicant: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude

Inventor： Antonio Sanchez ,  Jean-Marc Girard ,  Gennadiy Itov ,  Manish Khandelwal ,  Matthew Damien Stephens ,  Peng Zhang

IPC: C07F7/02 ,  C07F7/10 ,  H01L21/02

CPC classification number: C07F7/025 ,  C07F7/10 ,  H01L21/02219 ,  H01L21/02617

Abstract: Halogen free amine substituted trisilylamine and tridisilylamine compounds and a method of their preparation via dehydrogenative coupling between the corresponding unsubstituted trisilylames and amines catalyzed by transition metal catalysts is described. This new approach is based on the catalytic dehydrocoupling of a Si—H and a N—H moiety to form an Si—N containing compound and hydrogen gas. The process can be catalyzed by transition metal heterogenous catalysts such as Ru(0) on carbon, Pd(0) on MgO) as well as transition metal organometallic complexes that act as homogeneous catalysts. The —Si—N containing products are halide free. Such compounds can be useful for the deposition of thin films by chemical vapor deposition or atomic layer deposition of Si containing films.

公开(公告)号：US09920077B2

公开(公告)日：2018-03-20

申请号：US15025198

申请日：2014-09-19

Applicant: Antonio Sanchez ,  Jean-Marc Girard

Inventor： Antonio Sanchez ,  Jean-Marc Girard ,  Gennadiy Itov ,  Manish Khandelwal ,  Matthew Damien Stephens ,  Peng Zhang

IPC: C07F5/06 ,  C07F7/02 ,  C07F7/10 ,  H01L21/02

CPC classification number: C07F7/025 ,  C07F7/10 ,  H01L21/02219 ,  H01L21/02617

Abstract: Halogen free amine substituted trisilylamine and tridisilylamine compounds and a method of their preparation via de-hydrogenative coupling between the corresponding unsubstituted trisilylamines and amines catalyzed by transition metal catalysts is described. This new approach is based on the catalytic dehydrocoupling of a Si—H and a N—H moiety to form an Si—N containing compound and hydrogen gas. The process can be catalyzed by transition metal heterogenous catalysts such as Ru(0) on carbon, Pd(0) on MgO) as well as transition metal organometallic complexes that act as homogeneous catalysts. The —Si—N containing products are halide free. Such compounds can be useful for the deposition of thin films by chemical vapor deposition or atomic layer deposition of Si containing films.

公开(公告)号：US09852904B2

公开(公告)日：2017-12-26

申请号：US14813413

申请日：2015-07-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Tetsuhiro Tanaka

IPC: H01L21/441 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L29/04 ,  H01L29/26 ,  H01L29/78 ,  C23C14/08 ,  C23C14/34 ,  H01L29/49

CPC classification number: H01L21/02565 ,  C23C14/086 ,  C23C14/3414 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02592 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/441 ,  H01L21/47576 ,  H01L21/47635 ,  H01L29/045 ,  H01L29/26 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.