公开(公告)号：US20210327505A1

公开(公告)日：2021-10-21

申请号：US16336900

申请日：2018-06-07

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Yi LI ,  Zhuorui WANG ,  Xiangshui MIAO ,  Yaxiong ZHOU ,  Long CHENG

IPC: G11C13/00 ,  H03K19/21 ,  G06F7/48

Abstract: The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

公开(公告)号：US20170287558A1

公开(公告)日：2017-10-05

申请号：US15629714

申请日：2017-06-21

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Qun LIU ,  Tao ZHANG ,  Xiangshui MIAO ,  Yi LI ,  Yaxiong ZHOU ,  Tianpeng MIAO

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/77

Abstract: A processor including a computing and memory structure including X in number integration units and X in number communication units, and a control unit. The integration units are computing and memory units (CMUs), each computing and memory unit (CMU) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation. Each computing and memory unit includes M in number bit units and M−1 in number vertical line switches. Each bit unit includes a resistor, a horizontal line switch and N in number memristors. X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1.

公开(公告)号：US20160020766A1

公开(公告)日：2016-01-21

申请号：US14867030

申请日：2015-09-28

Applicant: Huazhong University of Science and Technology

Inventor： Xiangshui MIAO ,  Yaxiong ZHOU ,  Yi LI ,  Huajun SUN

IPC: H03K19/00 ,  H03K19/20

CPC classification number: H03K19/0002 ,  H03K19/0021 ,  H03K19/0813 ,  H03K19/20

Abstract: A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.

Abstract translation: 一种非易失性布尔逻辑运算电路，包括：两个输入端; 输出端 第一电阻式开关元件M1，第一电阻式开关元件M包括正极和负极; 和第二电阻开关元件M2，第二电阻开关元件M2包括正极和负极。 第一电阻式开关元件M1的负电极作为逻辑运算电路的第一输入端工作。 第二电阻开关元件M2的负极作为逻辑运算电路的第二输入端工作。 第二电阻开关元件M2的正极与第一电阻式开关元件M1的正极连接，其连接端作为逻辑运算电路的输出端。