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    REVERSIBLE LOGIC CIRCUIT AND OPERATION METHOD THEREOF
    1.
    发明申请
    REVERSIBLE LOGIC CIRCUIT AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20210218402A1

    公开(公告)日：2021-07-15

    申请号：US16965602

    申请日：2019-07-16

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Yi LI ,  Long CHENG ,  Xiangshui MIAO

    IPC: H03K19/173

    Abstract: A reversible logic circuit and an operation method thereof are provided. The logic circuit includes resistive switching cells, word lines, and bit lines. The word lines and the bit lines are perpendicular to each other. The anode of a resistive switching cell is connected to the word line as a first input terminal to apply logic operating voltage or be grounded. The cathode of a resistive switching cell is connected to the bit line as a second input terminal to apply logic operating voltage or be grounded. When performing reversible logic operation, four levels of resistance states of the resistive switching cell are used as logic outputs to implement single-input NOT and dual-input C-NOT reversible logic functions.

    NON-VOLATILE BOOLEAN LOGIC OPERATION CIRCUIT AND OPERATION METHOD THEREOF
    3.
    发明申请
    NON-VOLATILE BOOLEAN LOGIC OPERATION CIRCUIT AND OPERATION METHOD THEREOF 有权
    非挥发性BOOLEAN逻辑操作电路及其操作方法

    公开(公告)号：US20160020766A1

    公开(公告)日：2016-01-21

    申请号：US14867030

    申请日：2015-09-28

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiangshui MIAO ,  Yaxiong ZHOU ,  Yi LI ,  Huajun SUN

    IPC: H03K19/00 ,  H03K19/20

    CPC classification number: H03K19/0002 ,  H03K19/0021 ,  H03K19/0813 ,  H03K19/20

    Abstract: A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.

    Abstract translation: 一种非易失性布尔逻辑运算电路，包括：两个输入端; 输出端 第一电阻式开关元件M1，第一电阻式开关元件M包括正极和负极; 和第二电阻开关元件M2，第二电阻开关元件M2包括正极和负极。 第一电阻式开关元件M1的负电极作为逻辑运算电路的第一输入端工作。 第二电阻开关元件M2的负极作为逻辑运算电路的第二输入端工作。 第二电阻开关元件M2的正极与第一电阻式开关元件M1的正极连接，其连接端作为逻辑运算电路的输出端。

    MULTIPLIER AND OPERATION METHOD BASED ON 1T1R MEMORY
    5.
    发明申请
    MULTIPLIER AND OPERATION METHOD BASED ON 1T1R MEMORY 有权

    公开(公告)号：US20210090646A1

    公开(公告)日：2021-03-25

    申请号：US16971678

    申请日：2019-07-02

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Xiangshui MIAO ,  Yi LI ,  Xiaodi HUANG

    IPC: G11C13/00 ,  G11C7/10 ,  G06F7/523

    Abstract: The invention discloses a multiplier and an operation method based on 1T1R memory. The multiplier includes: a 1T1R crossbar A1, a 1T1R crossbar A2, a 1T1R crossbar A3, and a peripheral circuit. The 1T1R matrices are configured to realize operation and store result of it, and the peripheral circuit is configured to transfer data and control signals, thereby controlling the operation and storage process of the 1T1R matrices. An operation circuit is configured to respectively achieve NOR Boolean logic operations, two-bit binary multipliers, and optimization. The operation method corresponding to the operation circuit respectively completes the corresponding calculation and storage process by controlling an initialization resistance state of 1T1R devices, the size of a word line input signal, the size of a bit line input signal, and the size of a source line input signal.

    ASSOCIATIVE MEMORY CIRCUIT
    6.
    发明申请
    ASSOCIATIVE MEMORY CIRCUIT 有权
    相关记忆电路

    公开(公告)号：US20150131355A1

    公开(公告)日：2015-05-14

    申请号：US14601216

    申请日：2015-01-20

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiangshui MIAO ,  Yi LI ,  Lei XU ,  Yingpeng ZHONG

    IPC: G11C15/04 ,  G11C5/06

    CPC classification number: G11C15/046 ,  G11C11/54 ,  G11C13/0007

    Abstract: An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage.

    Abstract translation: 一种包括第一忆阻器，第二忆阻器，固定值电阻器R和操作比较器的关联存储器电路。 第一忆阻器的一个端子是相关存储器电路的第一输入端，并且第一忆阻器的另一端连接到操作比较器的第一输入端。 第二忆阻器的一个端子是关联存储器电路的第二输入端，并且第二忆阻器的另一端连接到运算比较器的第一输入端。 固定值电阻的一端连接到运算比较器的第一输入端，固定值电阻的另一端连接到地。 操作比较器的第二输入端连接到参考电压。

    MAX POOLING PROCESSOR BASED ON 1T1R MEMORY
    7.
    发明申请
    MAX POOLING PROCESSOR BASED ON 1T1R MEMORY 有权

    公开(公告)号：US20210224643A1

    公开(公告)日：2021-07-22

    申请号：US16631840

    申请日：2019-07-12

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Yi LI ,  Rui KUANG ,  Xiang-Shui MIAO

    IPC: G06N3/08 ,  G06N3/04 ,  G11C13/00

    Abstract: The present disclosure belongs to the technical field of artificial neural networks, and provides to a max pooling processor based on 1T1R memory, comprising an input module, a max pooling operation module, and an output module; the input module is configured to transmit an operating voltage according to the convolution result in the convolutional neural network; the 1T1R memory in the max pooling operation module is configured to adjust a conductance value of the RRAM according to the gate voltage of the transistor therein to achieve the max pooling operation by using the non-volatile multi-value conductance regulation characteristic of the RRAM, and store a max pooling result; and the output module is configured to read the max pooling result and output it.

    CONVOLUTIONAL NEURAL NETWORK ON-CHIP LEARNING SYSTEM BASED ON NON-VOLATILE MEMORY
    8.
    发明申请
    CONVOLUTIONAL NEURAL NETWORK ON-CHIP LEARNING SYSTEM BASED ON NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20200342301A1

    公开(公告)日：2020-10-29

    申请号：US16961932

    申请日：2019-07-12

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Xiangshui MIAO ,  Yi LI ,  Wenqian PAN

    IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06F17/15

    Abstract: Disclosed by the disclosure is a convolutional neural network on-chip learning system based on non-volatile memory, comprising: an input module, a convolutional neural network module, an output module and a weight update module. The on-chip learning of the convolutional neural network module implements a synaptic function by using a characteristic which the conductance of a memristor changes according to an applied pulse, and the convolutional kernel value or synaptic weight value is stored in a memristor unit; the input module converts an input signal into a voltage signal required by the convolutional neural network module; the convolutional neural network module converts the input voltage signal level by level, and transmits the result to the output module to obtain an output of the network; and the weight update module adjusts the conductance value of the memristor in the convolutional neural network module according to the result of the output module to update a network convolutional kernel value or synaptic weight value.

    MEMORY-BASED CONVOLUTIONAL NEURAL NETWORK SYSTEM
    9.
    发明申请
    MEMORY-BASED CONVOLUTIONAL NEURAL NETWORK SYSTEM 审中-公开

    公开(公告)号：US20200285954A1

    公开(公告)日：2020-09-10

    申请号：US16464977

    申请日：2018-06-07

    Applicant: Huazhong University of Science and Technology

    Inventor： Yi LI ,  Wenqian PAN ,  Xiangshui MIAO

    IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

    Abstract: The present disclosure discloses a memory-based CNN, comprising: an input module, a convolution layer circuit module, a pooling layer circuit module, an activation function module, a fully connected layer circuit module, a softmax function module and an output module, convolution kernel values or synapse weights are stored in the NOR FLASH units; the input module converts an input signal into a voltage signal required by the convolutional neural network; the convolutional layer circuit module convolves the voltage signal corresponding to the input signal with the convolution kernel values, and transmits the result to the activation function module; the activation function module activates the signal; the pooling layer circuit module performs a pooling operation on the activated signal; the fully connected layer circuit module multiplies the pooled signal with the synapse weights to achieve classification; the softmax function module normalizes the classification result into probability values as an output of the entire network. The disclosure satisfies the requirements of real-time data processing and has low hardware cost.

    PREPARATION METHOD OF BIPOLAR GATING MEMRISTOR AND BIPOLAR GATING MEMRISTOR
    10.
    发明公开
    PREPARATION METHOD OF BIPOLAR GATING MEMRISTOR AND BIPOLAR GATING MEMRISTOR 审中-公开

    公开(公告)号：US20230301215A1

    公开(公告)日：2023-09-21

    申请号：US17785916

    申请日：2021-08-30

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Yi LI ,  Yuhui HE ,  Yaoyao FU ,  Xiaodi HUANG ,  Xiangshui MIAO

    IPC: H10N70/00 ,  H10N70/20 ,  H10B63/00

    CPC classification number: H10N70/826 ,  H10B63/22 ,  H10B63/84 ,  H10N70/026 ,  H10N70/245

    Abstract: The present invention provides a preparation method of a bipolar gating memristor and a bipolar gating memristor. The preparation method includes: preparing a lower electrode; depositing a resistive material layer on the lower electrode; and depositing an upper electrode on the resistive material layer by using a magnetron sputtering manner to deposit the upper electrode, controlling upper electrode metal particles to have suitable kinetic energy by controlling sputtering power, controlling a vacuum degree of a region where the upper electrode and the resistive material layer are located, such that a redox reaction occurs spontaneously between the upper electrode and the resistive material layer during the deposition of the upper electrode to form a built-in bipolar gating layer; and continuously depositing the upper electrode on the built-in bipolar gating layer .

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