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公开(公告)号：US09280343B2
公开(公告)日：2016-03-08
申请号：US12538717
申请日：2009-08-10
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/522
摘要： Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.
摘要翻译： 本发明的一些实施例提供了一种用于操作存储队列的系统，其中存储队列缓冲正在等待被提交到处理器中的存储器系统的存储。 在操作期间，系统检查商店队列头部的条目。 如果条目包含一个签名，系统将检查一个未确认的计数器，该计数器可以跟踪从存储队列发送到内存系统但尚未被确认为提交到内存系统的存储操作数。 如果未确认的计数器不为零，则系统将等待直到未确认的计数器等于零，然后从存储队列中删除该元素令牌。
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公开(公告)号：US08732407B2
公开(公告)日：2014-05-20
申请号：US12273697
申请日：2008-11-19
CPC分类号： G06F9/3824 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.
摘要翻译： 本发明的一些实施例提供了一种在尝试在高速缓存行上获取存储标记时避免死锁的系统。 在操作期间，系统跟踪在执行线程期间出现的存储标记请求，其中高速缓存行上的存储标记指示一个或多个关联的存储缓冲器条目正在等待被提交到高速缓存行。 在该系统中，存储标记请求以流水线方式处理，这允许在对同一线程完成的先前存储标记请求之前启动存储标记请求。 接下来，如果存储标记请求失败，则在有限的时间内，系统会删除或防止与同一线程的较小的存储标记请求相关联的存储标记，从而避免当一个或多个其他 线程尝试存储标记相同的缓存行。
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公开(公告)号：US20100125707A1
公开(公告)日：2010-05-20
申请号：US12273697
申请日：2008-11-19
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.
摘要翻译： 本发明的一些实施例提供了一种在尝试在高速缓存行上获取存储标记时避免死锁的系统。 在操作期间，系统跟踪在执行线程期间出现的存储标记请求，其中高速缓存行上的存储标记指示一个或多个关联的存储缓冲器条目正在等待被提交到高速缓存行。 在该系统中，存储标记请求以流水线方式处理，这允许在对同一线程完成的先前存储标记请求之前启动存储标记请求。 接下来，如果存储标记请求失败，则在有限的时间内，系统会删除或防止与同一线程的较小的存储标记请求相关联的存储标记，从而避免当一个或多个其他 线程尝试存储标记相同的缓存行。
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4.发明申请DYNAMICALLY CONFIGURING MEMORY INTERLEAVING FOR LOCALITY AND PERFORMANCE ISOLATION 审中-公开动态配置内存与本地化和性能隔离的交互公开(公告)号：US20100325374A1
公开(公告)日：2010-12-23
申请号：US12486138
申请日：2009-06-17
CPC分类号： G06F12/0607 , G06F12/0646 , G06F12/0813 , G06F12/0817 , G06F12/10
摘要： Embodiments of the present invention provide a system that dynamically reconfigures memory. During operation, the system determines that a virtual memory page is to be reconfigured from an original virtual-address-to-physical-address mapping to a new virtual-address-to-physical-address mapping. The system then determines a new real address mapping for a set of virtual addresses in the virtual memory page by selecting a range of real addresses for the virtual addresses that are arranged according to the new virtual-address-to-physical-address mapping. Next, the system temporarily disables accesses to the virtual memory page. Then, the system copies data from real address locations indicated by the original virtual-address-to-physical-address mapping to real address locations indicated by the new virtual-address-to-physical-address mapping. Next, the system updates the real-address-to-physical-address mapping for the page, and re-enables accesses to the virtual memory page.
摘要翻译： 本发明的实施例提供一种动态重新配置存储器的系统。 在操作期间，系统确定虚拟内存页面将被重新配置为从原始虚拟地址到物理地址映射到新的虚拟地址到物理地址映射。 然后，系统通过选择根据新的虚拟地址到物理地址映射排列的虚拟地址的实际地址的范围来确定虚拟存储器页面中的一组虚拟地址的新的真实地址映射。 接下来，系统暂时禁用对虚拟内存页的访问。 然后，系统将由原始虚拟地址到物理地址映射指示的实际地址位置的数据复制到由新的虚拟地址到物理地址映射指示的实际地址位置。 接下来，系统更新页面的实际地址到物理地址映射，并重新启用对虚拟内存页的访问。
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公开(公告)号：US20110035561A1
公开(公告)日：2011-02-10
申请号：US12538717
申请日：2009-08-10
IPC分类号： G06F12/02
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/522
摘要： Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.
摘要翻译： 本发明的一些实施例提供了一种用于操作存储队列的系统，其中存储队列缓冲正在等待被提交到处理器中的存储器系统的存储。 在操作期间，系统检查商店队列头部的条目。 如果条目包含一个签名，系统将检查一个未确认的计数器，该计数器可以跟踪从存储队列发送到内存系统但尚未被确认为提交到内存系统的存储操作数。 如果未确认的计数器不为零，则系统将等待直到未确认的计数器等于零，然后从存储队列中删除该元素令牌。
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公开(公告)号：US07797491B2
公开(公告)日：2010-09-14
申请号：US11591225
申请日：2006-10-31
CPC分类号： G06F12/0842 , G06F9/3004 , G06F9/383 , G06F9/3834 , G06F9/3851
摘要： One embodiment of the present invention provides a system that facilitates load reordering through cacheline marking. During operation, the system receives a load operation to be executed. Next, the system determines whether a cacheline for the load has been load-marked by a thread which is performing the load. If so, the system performs the load. Otherwise, the system obtains the cacheline and subsequently attempts to load-mark the cacheline. If the cacheline is successfully load-marked, the system performs the load.
摘要翻译： 本发明的一个实施例提供一种通过高速缓存行标记来促进负载重新排序的系统。 在操作期间，系统接收要执行的加载操作。 接下来，系统确定负载的高速缓存线是否由正在执行负载的线程加载标记。 如果是这样，系统执行负载。 否则，系统将获取缓存线，并随后尝试加载标记缓存线。 如果缓存线已成功加载标记，系统将执行加载。
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公开(公告)号：US07594100B2
公开(公告)日：2009-09-22
申请号：US11540257
申请日：2006-09-29
CPC分类号： G06F9/3834 , G06F9/3824 , G06F9/3826 , G06F9/3867 , G06F12/0897
摘要： One embodiment of the present invention provides a store queue that applies the stores to a memory subsystem in program order. This store queue includes a content-addressable memory (CAM), which holds pending stores and facilitates looking up stores based on addresses for the stores, wherein the CAM does not keep track of program order between stores to different addresses. The store queue also includes a program-order queue which keeps track of program order between the stores in the CAM and thereby facilitates applying the stores to the memory subsystem in program order. In a variation on this embodiment, the CAM is a priority CAM which holds separate copies of multiple stores with identical addresses, and when a lookup based on an address matches multiple stores, returns the youngest matching store.
摘要翻译： 本发明的一个实施例提供一种存储队列，其以程序顺序将存储应用于存储器子系统。 该存储队列包括内容可寻址存储器（CAM），其保存挂起的存储并且便于基于用于存储的地址来查找存储，其中，CAM不会将存储之间的程序顺序跟踪到不同的地址。 存储队列还包括程序顺序队列，其跟踪CAM中的存储之间的程序顺序，从而有助于以程序顺序将存储应用于存储器子系统。 在本实施例的变型中，CAM是优先CAM，其保存具有相同地址的多个商店的分开的副本，并且当基于地址的查找匹配多个商店时，返回最年轻的匹配商店。
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8.发明申请METHOD AND APPARATUS FOR TRACKING LOAD-MARKS AND STORE-MARKS ON CACHE LINES 有权用于跟踪缓存行上的负载标记和存储标记的方法和装置公开(公告)号：US20090113131A1
公开(公告)日：2009-04-30
申请号：US11924742
申请日：2007-10-26
CPC分类号： G06F12/0897 , G06F12/0842 , G06F12/126
摘要： Embodiments of the present invention provide a system that handles load-marked and store-marked cache lines. Upon asserting a load-mark or a store-mark for a cache line during a given phase of operation, the system adds an entry to a private buffer and in doing so uses an address of the cache line as a key for the entry in the private buffer. The system also updates the entry in the private buffer with information about the load-mark or store-mark and uses pointers for the entry and for the last entry added to the private buffer to add the entry to a sequence of private buffer entries placed during the phase of operation. The system then uses the entries in the private buffer to remove the load-marks and store-marks from cache lines when the phase of operation is completed.
摘要翻译： 本发明的实施例提供一种处理负载标记和存储标记的高速缓存行的系统。 在给定的操作阶段中断定高速缓存行的加载标记或存储标记时，系统将一个条目添加到专用缓冲区，并且在这样做时使用高速缓存行的地址作为该条目的密钥 私人缓存。 系统还使用有关加载标记或存储标记的信息更新专用缓冲区中的条目，并使用条目的指针和添加到专用缓冲区的最后一个条目将条目添加到放置在 操作阶段。 当操作阶段完成时，系统将使用专用缓冲区中的条目从缓存行中删除加载标记和存储标记。
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9.发明申请公开(公告)号：US20090019272A1
公开(公告)日：2009-01-15
申请号：US11774705
申请日：2007-07-09
IPC分类号： G06F9/312
CPC分类号： G06F9/3834 , G06F9/3842
摘要： Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue during a speculative execution mode. If an entry for the store does not already exist in the store queue, the system writes the store into an available entry in the store queue and updates a byte mask for the entry. Otherwise, if an entry for the store already exists in the store queue, the system merges the store into the existing entry in the store queue and updates the byte mask for the entry to include information about the newly merged store. The system then forwards the data from the store queue to subsequent dependent loads.
摘要翻译： 本发明的实施例提供一种缓冲存储在支持推测执行的处理器上的系统的系统。 在推测执行模式期间，系统通过将存储缓存到存储队列中的条目来启动。 如果商店中的条目不存在于商店队列中，则系统将商店写入存储队列中的可用条目，并更新条目的字节掩码。 否则，如果商店的条目已经存在于存储队列中，则系统将存储合并到存储队列中的现有条目中，并更新条目的字节掩码以包括关于新合并存储的信息。 然后，系统将数据从存储队列转发到后续的相关负载。
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公开(公告)号：US20080082738A1
公开(公告)日：2008-04-03
申请号：US11540257
申请日：2006-09-29
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3824 , G06F9/3826 , G06F9/3867 , G06F12/0897
摘要： One embodiment of the present invention provides a store queue that applies the stores to a memory subsystem in program order. This store queue includes a content-addressable memory (CAM), which holds pending stores and facilitates looking up stores based on addresses for the stores, wherein the CAM does not keep track of program order between stores to different addresses. The store queue also includes a program-order queue which keeps track of program order between the stores in the CAM and thereby facilitates applying the stores to the memory subsystem in program order. In a variation on this embodiment, the CAM is a priority CAM which holds separate copies of multiple stores with identical addresses, and when a lookup based on an address matches multiple stores, returns the youngest matching store.
摘要翻译： 本发明的一个实施例提供一种存储队列，其以程序顺序将存储应用于存储器子系统。 该存储队列包括内容可寻址存储器（CAM），其保存挂起的存储并且便于基于用于存储的地址来查找存储，其中，CAM不会将存储之间的程序顺序跟踪到不同的地址。 存储队列还包括程序顺序队列，其跟踪CAM中的存储之间的程序顺序，从而有助于以程序顺序将存储应用于存储器子系统。 在本实施例的变型中，CAM是优先CAM，其保存具有相同地址的多个商店的分开的副本，并且当基于地址的查找匹配多个商店时，返回最年轻的匹配商店。
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