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1.发明申请DYNAMICALLY CONFIGURING MEMORY INTERLEAVING FOR LOCALITY AND PERFORMANCE ISOLATION 审中-公开动态配置内存与本地化和性能隔离的交互公开(公告)号：US20100325374A1
公开(公告)日：2010-12-23
申请号：US12486138
申请日：2009-06-17
CPC分类号： G06F12/0607 , G06F12/0646 , G06F12/0813 , G06F12/0817 , G06F12/10
摘要： Embodiments of the present invention provide a system that dynamically reconfigures memory. During operation, the system determines that a virtual memory page is to be reconfigured from an original virtual-address-to-physical-address mapping to a new virtual-address-to-physical-address mapping. The system then determines a new real address mapping for a set of virtual addresses in the virtual memory page by selecting a range of real addresses for the virtual addresses that are arranged according to the new virtual-address-to-physical-address mapping. Next, the system temporarily disables accesses to the virtual memory page. Then, the system copies data from real address locations indicated by the original virtual-address-to-physical-address mapping to real address locations indicated by the new virtual-address-to-physical-address mapping. Next, the system updates the real-address-to-physical-address mapping for the page, and re-enables accesses to the virtual memory page.
摘要翻译： 本发明的实施例提供一种动态重新配置存储器的系统。 在操作期间，系统确定虚拟内存页面将被重新配置为从原始虚拟地址到物理地址映射到新的虚拟地址到物理地址映射。 然后，系统通过选择根据新的虚拟地址到物理地址映射排列的虚拟地址的实际地址的范围来确定虚拟存储器页面中的一组虚拟地址的新的真实地址映射。 接下来，系统暂时禁用对虚拟内存页的访问。 然后，系统将由原始虚拟地址到物理地址映射指示的实际地址位置的数据复制到由新的虚拟地址到物理地址映射指示的实际地址位置。 接下来，系统更新页面的实际地址到物理地址映射，并重新启用对虚拟内存页的访问。
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公开(公告)号：US09280343B2
公开(公告)日：2016-03-08
申请号：US12538717
申请日：2009-08-10
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/522
摘要： Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.
摘要翻译： 本发明的一些实施例提供了一种用于操作存储队列的系统，其中存储队列缓冲正在等待被提交到处理器中的存储器系统的存储。 在操作期间，系统检查商店队列头部的条目。 如果条目包含一个签名，系统将检查一个未确认的计数器，该计数器可以跟踪从存储队列发送到内存系统但尚未被确认为提交到内存系统的存储操作数。 如果未确认的计数器不为零，则系统将等待直到未确认的计数器等于零，然后从存储队列中删除该元素令牌。
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公开(公告)号：US08732407B2
公开(公告)日：2014-05-20
申请号：US12273697
申请日：2008-11-19
CPC分类号： G06F9/3824 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.
摘要翻译： 本发明的一些实施例提供了一种在尝试在高速缓存行上获取存储标记时避免死锁的系统。 在操作期间，系统跟踪在执行线程期间出现的存储标记请求，其中高速缓存行上的存储标记指示一个或多个关联的存储缓冲器条目正在等待被提交到高速缓存行。 在该系统中，存储标记请求以流水线方式处理，这允许在对同一线程完成的先前存储标记请求之前启动存储标记请求。 接下来，如果存储标记请求失败，则在有限的时间内，系统会删除或防止与同一线程的较小的存储标记请求相关联的存储标记，从而避免当一个或多个其他 线程尝试存储标记相同的缓存行。
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公开(公告)号：US20100125707A1
公开(公告)日：2010-05-20
申请号：US12273697
申请日：2008-11-19
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.
摘要翻译： 本发明的一些实施例提供了一种在尝试在高速缓存行上获取存储标记时避免死锁的系统。 在操作期间，系统跟踪在执行线程期间出现的存储标记请求，其中高速缓存行上的存储标记指示一个或多个关联的存储缓冲器条目正在等待被提交到高速缓存行。 在该系统中，存储标记请求以流水线方式处理，这允许在对同一线程完成的先前存储标记请求之前启动存储标记请求。 接下来，如果存储标记请求失败，则在有限的时间内，系统会删除或防止与同一线程的较小的存储标记请求相关联的存储标记，从而避免当一个或多个其他 线程尝试存储标记相同的缓存行。
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公开(公告)号：US20110035561A1
公开(公告)日：2011-02-10
申请号：US12538717
申请日：2009-08-10
IPC分类号： G06F12/02
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/522
摘要： Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.
摘要翻译： 本发明的一些实施例提供了一种用于操作存储队列的系统，其中存储队列缓冲正在等待被提交到处理器中的存储器系统的存储。 在操作期间，系统检查商店队列头部的条目。 如果条目包含一个签名，系统将检查一个未确认的计数器，该计数器可以跟踪从存储队列发送到内存系统但尚未被确认为提交到内存系统的存储操作数。 如果未确认的计数器不为零，则系统将等待直到未确认的计数器等于零，然后从存储队列中删除该元素令牌。
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6.发明申请SUPPORTING EFFICIENT SPIN-LOCKS AND OTHER TYPES OF SYNCHRONIZATION IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM 有权在高速缓存多媒体系统中支持有效的旋转锁和其他类型的同步公开(公告)号：US20100332766A1
公开(公告)日：2010-12-30
申请号：US12492946
申请日：2009-06-26
申请人： Haakan E. Zeffer , Robert E. Cypher
发明人： Haakan E. Zeffer , Robert E. Cypher
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/526 , G06F12/0815
摘要： Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that the lock is currently held by another thread, the system periodically executes an instruction that tests a status of the lock. If the status indicates the lock is valid, the system continues to test the status of the lock. Otherwise, if the status indicates that the lock was invalidated by a store, the system attempts to acquire the lock by executing an atomic operation. On the other hand, if the status indicates that the lock was invalidated by an atomic operation, or that the lock is not present in the cache, the system repeats the loading and reading operations.
摘要翻译： 本发明的一些实施例提供一种获取共享存储器多处理器系统中的锁定的系统。 在操作期间，系统将锁加载到与线程相关联的缓存中，然后读取锁的值。 如果该值表示该锁当前由另一个线程持有，则系统会定期执行一个测试锁定状态的指令。 如果状态表示锁定有效，系统将继续测试锁的状态。 否则，如果状态指示锁定被存储无效，系统将尝试通过执行原子操作获取锁定。 另一方面，如果状态指示锁被原子操作无效，或者锁不存在于高速缓存中，则系统重复加载和读取操作。
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公开(公告)号：US20100153655A1
公开(公告)日：2010-06-17
申请号：US12335019
申请日：2008-12-15
申请人： Robert E. Cypher , Haakan E. Zeffer
发明人： Robert E. Cypher , Haakan E. Zeffer
IPC分类号： G06F12/08
CPC分类号： G06F9/3834 , G06F9/3851 , G06F12/0842 , G06F12/0855
摘要： Some embodiments of the present invention provide a system that performs stores in a memory system. During operation, the system performs a store for a first thread, which involves creating an entry for the store in a store queue for the first thread. It also involves attempting to store-mark a corresponding cache line for the first thread by sending a store-mark request for the first thread to the memory system, wherein a store-mark on the cache line indicates that one or more store queue entries are waiting to be committed to the cache line. If the attempt to store-mark the cache line fails because a second thread holds a store-mark on the cache line, and if obtaining the store-mark will ensure forward progress for the first thread, the system forces the second thread to release the store-mark, so the first thread can acquire a store-mark for the cache line.
摘要翻译： 本发明的一些实施例提供一种在存储系统中执行存储的系统。 在操作期间，系统执行第一个线程的存储，其涉及为第一线程的存储队列中的商店创建条目。 它还涉及通过向存储系统发送针对第一线程的存储标记请求来尝试存储对第一线程的对应高速缓存线，其中高速缓存线上的存储标记指示一个或多个存储队列条目是 等待被提交到缓存行。 如果存储标记缓存行的尝试失败，因为第二个线程在高速缓存行上保存存储标记，并且如果获取存储标记将确保第一个线程的前进进程，则系统强制第二个线程释放 存储标记，所以第一个线程可以获取高速缓存行的存储标记。
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公开(公告)号：US08516199B2
公开(公告)日：2013-08-20
申请号：US12405483
申请日：2009-03-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F2212/1041
摘要： Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.
摘要翻译： 本发明的一些实施例提供了一种在支持基于目录的高速缓存相干方案的多处理器系统中处理对高速缓存行的请求的系统。 在操作期间，系统从家庭节点处的请求节点接收对高速缓存行的请求，其中家庭节点维护包括高速缓存行的地址空间的全部或子集的目录信息。 接下来，系统在家庭节点处执行动作，这导致高速缓存行的有效副本被发送到请求节点。 然后，系统在家庭节点处完成对请求的处理，而不等待指示请求节点接收到高速缓存行的有效副本的确认。
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公开(公告)号：US08117393B2
公开(公告)日：2012-02-14
申请号：US12270685
申请日：2008-11-13
申请人： Robert E. Cypher , Haakan E. Zeffer
发明人： Robert E. Cypher , Haakan E. Zeffer
CPC分类号： G06F12/0897
摘要： Embodiments of the present invention provide a system that selectively performs lookups for cache lines. During operation, the system by maintains a lower-level cache and a higher-level cache in accordance with a set of rules that dictate conditions under which cache lines are held in the lower-level cache and the higher-level cache. The system next performs a lookup for cache line A in the lower level cache. The system then discovers that the lookup for cache line A missed in the lower-level cache, but that cache line B is present in the lower-level cache. Next, in accordance with the set of rules, the system determines, without performing a lookup for cache line A in the higher-level cache, that cache line A is guaranteed not to be present and valid in the higher-level cache because cache line B is present in the lower-level cache.
摘要翻译： 本发明的实施例提供了一种选择性地执行对高速缓存行的查找的系统。 在操作期间，系统通过根据一组规则来维护低级缓存和更高级别的高速缓存，这些规则规定了缓存行被保存在下级高速缓存和高级缓存中的条件。 该系统接下来对下一级缓存中的高速缓存行A进行查找。 然后，系统发现在低级缓存中缺少高速缓存行A的查找，但是该高速缓存行B存在于下级高速缓存中。 接下来，根据规则集，系统在不执行对高级缓存中的高速缓存行A的查找的情况下确定该高速缓存行A被保证不在高级缓存中存在且有效，因为高速缓存行 B存在于低级缓存中。
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公开(公告)号：US08103834B2
公开(公告)日：2012-01-24
申请号：US12260220
申请日：2008-10-29
申请人： Robert E. Cypher , Haakan E. Zeffer
发明人： Robert E. Cypher , Haakan E. Zeffer
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F2212/502
摘要： Embodiments of the present invention provide a system that maintains coherence between cache lines in a computer system by using dynamic privatization. During operation, the system starts by receiving a request for a read-only copy of a cache line from a processor. The system then determines if the processor has privately requested the cache line a predetermined number of times. If so, the system provides a copy of the cache line to the processor in an exclusive state. Otherwise, the system provides a copy of the cache line to the processor in a shared state.
摘要翻译： 本发明的实施例提供一种通过使用动态私有化来维持计算机系统中的高速缓存行之间的一致性的系统。 在操作期间，系统从处理器接收到对高速缓存行的只读副本的请求开始。 然后，系统确定处理器是否已经私人地请求高速缓存行预定次数。 如果是这样，系统会以独占状态向处理器提供高速缓存行的副本。 否则，系统将共享状态的缓存行的副本提供给处理器。
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