公开(公告)号：US20130240990A1

公开(公告)日：2013-09-19

申请号：US13989808

申请日：2011-12-02

申请人： Haizhou Yin ,  Wei Jiang ,  Gaobo Xu

发明人： Haizhou Yin ,  Wei Jiang ,  Gaobo Xu

IPC分类号： H01L29/40 ,  H01L29/417

CPC分类号： H01L29/401 ,  H01L21/28185 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

摘要： A method for manufacturing a semiconductor structure and a semiconductor device manufactured using the same are disclosed. In replacement gate process, the present invention is capable of reducing contact resistance at source/drain regions through forming doped amorphous Si layers above source/drain regions, forming contact holes (310) penetrating through the interlayer dielectric layer (300) and amorphous Si layers (251); wherein the contact holes (310) at least expose part of the source/drain regions (110), and contact layers are formed at the exposed area of the source/drain regions and sidewalls of the contact holes in the amorphous Si layer. Since contact layers are formed after high-k dielectric layer has been annealed, metal silicide layers are protected from damages at high temperatures.

摘要翻译： 公开了一种用于制造半导体结构的方法和使用其制造的半导体器件。 在替代栅极工艺中，本发明能够通过在源极/漏极区域之上形成掺杂的非晶Si层来形成源极/漏极区域的接触电阻，形成穿过层间介质层（300）的接触孔（310）和非晶Si层 （251）; 其中所述接触孔（310）至少暴露所述源极/漏极区域（110）的部分以及所述接触层在所述非晶硅层中的所述源极/漏极区域和所述接触孔的侧壁的暴露区域处形成。 由于在高k电介质层退火之后形成接触层，因此金属硅化物层在高温下被保护免受损坏。

公开(公告)号：US20140299919A1

公开(公告)日：2014-10-09

申请号：US14354648

申请日：2012-07-31

申请人： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

发明人： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer on the substrate; forming a spacer on opposite sides of the sacrificial gate stack; and forming source/drain regions with the spacer as a mask.

摘要翻译： 提供半导体器件及其制造方法。 在一个实施例中，该方法包括：在衬底上生长第一外延层; 在所述第一外延层上形成牺牲栅叠层; 选择性地蚀刻第一外延层; 在衬底上生长并原位掺杂第二外延层; 在所述牺牲栅极堆叠的相对侧上形成间隔物; 以及用间隔物形成源极/漏极区域作为掩模。

公开(公告)号：US20130307034A1

公开(公告)日：2013-11-21

申请号：US13640735

申请日：2012-05-17

申请人： Haizhou Yin ,  Wei Jiang

发明人： Haizhou Yin ,  Wei Jiang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： A method of manufacturing a semiconductor structure, which comprises the steps of: providing a substrate, forming a fin on the substrate, which comprises a central portion for forming a channel and an end portion for forming a source/drain region and a source/drain extension region; forming a gate stack to cover the central portion of the fin; performing light doping to form a source/drain extension region in the end portion of the fin; forming a spacer on sidewalls of the gate stack; performing heavy doping to form a source/drain region in the end portion of the fin; removing at least a part of the spacer to expose at least a part of the source/drain extension region; forming a contact layer on an upper surface of the source/drain region and an exposed area of the source/drain extension region. Correspondingly, the present invention also provides a semiconductor structure. By forming a thin contact layer in the source/drain extension region, the present invention can not only effectively reduce the contact resistance of the source/drain extension region, but also effectively control the junction depth of the source/drain extension region by controlling the thickness of the contact layer, thereby suppressing the short channel effect.

摘要翻译： 一种制造半导体结构的方法，包括以下步骤：提供衬底，在衬底上形成翅片，其包括用于形成沟道的中心部分和用于形成源极/漏极区域的端部和源极/漏极 延伸区域 形成栅极堆叠以覆盖鳍片的中心部分; 执行轻掺杂以在鳍的端部形成源/漏延伸区; 在所述栅极堆叠的侧壁上形成间隔物; 进行重掺杂以在鳍的端部形成源/漏区; 去除所述间隔物的至少一部分以暴露所述源极/漏极延伸区域的至少一部分; 在源极/漏极区域的上表面和源极/漏极延伸区域的暴露区域上形成接触层。 相应地，本发明还提供一种半导体结构。 通过在源极/漏极延伸区域中形成薄的接触层，本发明不仅可以有效地降低源极/漏极延伸区域的接触电阻，而且可以通过控制源极/漏极延伸区域的结深度来有效地控制源极/漏极延伸区域的结深度 接触层的厚度，从而抑制短沟道效应。

公开(公告)号：US08530328B1

公开(公告)日：2013-09-10

申请号：US13512326

申请日：2012-05-26

申请人： Haizhou Yin ,  Wei Jiang

发明人： Haizhou Yin ,  Wei Jiang

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a first shallow trench isolation in a substrate; forming a semiconductor device structure in an active region surrounded by the first shallow trench isolation; removing the first shallow trench isolation and leaving a shallow trench in the substrate; and filling the shallow trench with an insulating material to form a second shallow trench isolation. In the method for manufacturing the semiconductor device according to the present invention, after forming the shallow trench isolation with high stress, the high stress is memorized by the gate to enhance the stress in the channel region by etching, removing, and then backfilling the shallow trench isolation, so that the carrier mobility in the channel regions to be formed later can be increased and the device performance can be improved.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括：在衬底中形成第一浅沟槽隔离; 在由所述第一浅沟槽隔离围绕的有源区域中形成半导体器件结构; 去除第一浅沟槽隔离并在衬底中留下浅沟槽; 并用绝缘材料填充浅沟槽以形成第二浅沟槽隔离。 在根据本发明的半导体器件的制造方法中，在形成具有高应力的浅沟槽隔离之后，通过栅极存储高应力，以通过蚀刻，去除，然后回填浅层来增强沟道区域中的应力 沟槽隔离，从而可以提高稍后形成的沟道区域中的载流子迁移率，并且可以提高器件性能。

公开(公告)号：US20130256845A1

公开(公告)日：2013-10-03

申请号：US13512330

申请日：2012-04-09

申请人： Haizhou Yin ,  Wei Jiang

发明人： Haizhou Yin ,  Wei Jiang

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L29/7833

摘要： The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability.

摘要翻译： 本发明公开了一种半导体器件，其包括：衬底和衬底中的浅沟槽隔离，其特征在于，所述半导体器件还包括在所述衬底和所述浅沟槽隔离之间的应力释放层。 在根据本发明的半导体器件及其制造方法中，通过在衬底和STI之间插入由较软材料制成的应力释放层，可以释放在形成STI期间累积的应力，从而减少 器件基板的漏电流，提高器件的可靠性。

公开(公告)号：US20130256810A1

公开(公告)日：2013-10-03

申请号：US13512329

申请日：2012-04-09

申请人： Haizhou Yin ,  Wei Jiang

发明人： Haizhou Yin ,  Wei Jiang

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L29/0638 ,  H01L29/7833

摘要： The present invention discloses a semiconductor device, which comprises: a first epitaxial layer on a substrate; a second epitaxial layer on the first epitaxial layer, wherein a MOSFET is formed in an active region of the second epitaxial layer; and an inverted-T shaped STI formed in the first epitaxial layer and the second epitaxial layer and surrounding the active region. In the semiconductor device and the method for manufacturing the same according to the present invention, the double epitaxial layers are selectively etched to form an inverted-T shaped STI, which effectively reduces the leakage current of the device without reducing the area of the active region, thereby improving the device reliability.

摘要翻译： 本发明公开了一种半导体器件，其包括：衬底上的第一外延层; 在所述第一外延层上的第二外延层，其中在所述第二外延层的有源区中形成MOSFET; 以及形成在第一外延层和第二外延层中并围绕有源区的倒T形STI。 在根据本发明的半导体器件及其制造方法中，选择性地蚀刻双重外延层以形成倒T形STI，其有效地减少器件的漏电流而不减少有源区的面积 ，从而提高了设备​​的可靠性。

公开(公告)号：US09147762B2

公开(公告)日：2015-09-29

申请号：US14354648

申请日：2012-07-31

申请人： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

发明人： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

IPC分类号： H01L27/01 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer on the substrate; forming a spacer on opposite sides of the sacrificial gate stack; and forming source/drain regions with the spacer as a mask.

摘要翻译： 提供半导体器件及其制造方法。 在一个实施例中，该方法包括：在衬底上生长第一外延层; 在所述第一外延层上形成牺牲栅叠层; 选择性地蚀刻第一外延层; 在衬底上生长并原位掺杂第二外延层; 在所述牺牲栅极堆叠的相对侧上形成间隔物; 以及用间隔物形成源极/漏极区域作为掩模。

公开(公告)号：US08889554B2

公开(公告)日：2014-11-18

申请号：US13380486

申请日：2011-04-18

申请人： Haizhou Yin ,  Wei Jiang ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Wei Jiang ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/41775 ,  H01L29/456 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure. The present invention is beneficial to the suppression of the diffusion of corresponding compositions from the contact layers into the channel region, reduction of the short channel effects, and improvement of the reliability of the semiconductor structure.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括：在第一间隔物的暴露的有源区上形成第一接触层; 在所述第一接触层的靠近栅极堆叠的区域处形成第二间隔物以部分地覆盖所述暴露的有源区; 在未覆盖的暴露的有源区中形成第二接触层，其中当第一接触层的扩散系数与第二接触层的扩散系数相同时，第一接触层的厚度小于第二接触层的厚度; 并且当第一接触层的扩散系数与第二接触层的扩散系数不同时，第一接触层的扩散系数小于第二接触层的扩散系数。 相应地，本发明还提供一种半导体结构。 本发明有利于抑制相应组合物从接触层扩散到沟道区中，减少短沟道效应，提高半导体结构的可靠性。

公开(公告)号：US08829642B2

公开(公告)日：2014-09-09

申请号：US13512330

申请日：2012-04-09

申请人： Haizhou Yin ,  Wei Jiang

发明人： Haizhou Yin ,  Wei Jiang

IPC分类号： H01L21/76 ,  H01L29/02

CPC分类号： H01L21/76232 ,  H01L29/7833

摘要： The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability.

摘要翻译： 本发明公开了一种半导体器件，其包括：衬底和衬底中的浅沟槽隔离，其特征在于，所述半导体器件还包括在所述衬底和所述浅沟槽隔离之间的应力释放层。 在根据本发明的半导体器件及其制造方法中，通过在衬底和STI之间插入由较软材料制成的应力释放层，可以释放在形成STI期间累积的应力，从而减少 器件基板的漏电流，提高器件的可靠性。

公开(公告)号：US20130260532A1

公开(公告)日：2013-10-03

申请号：US13512331

申请日：2012-04-09

申请人： Haizhou Yin ,  Wei Jiang

发明人： Haizhou Yin ,  Wei Jiang

IPC分类号： H01L21/762

CPC分类号： H01L21/26506 ,  H01L21/76237 ,  H01L21/76283 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a shallow trench in a substrate; forming a shallow trench filling layer in the shallow trench; forming a cap layer on the shallow trench filling layer; and implanting ions into the shallow trench filling layer and performing an annealing to form a shallow trench isolation. In the method for manufacturing the semiconductor device according to the present invention, an insulating material is formed by implanting ions into the filling material in the shallow trench, and a compressive stress is applied to the active region of the substrate due to the volume expansion of the filling material, so that the carrier mobility in the channel regions to be formed later can be increased and the device performance can be improved.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括：在衬底中形成浅沟槽; 在浅沟槽中形成浅沟槽填充层; 在浅沟槽填充层上形成盖层; 并将离子注入到浅沟槽填充层中并执行退火以形成浅沟槽隔离。 在根据本发明的半导体器件的制造方法中，通过将离子注入到浅沟槽中的填充材料中形成绝缘材料，并且由于体积膨胀而将压缩应力施加到衬底的有源区域 填充材料，从而可以提高稍后形成的沟道区域中的载流子迁移率，并且可以提高器件性能。