公开(公告)号：US20130240990A1

公开(公告)日：2013-09-19

申请号：US13989808

申请日：2011-12-02

申请人： Haizhou Yin ,  Wei Jiang ,  Gaobo Xu

发明人： Haizhou Yin ,  Wei Jiang ,  Gaobo Xu

IPC分类号： H01L29/40 ,  H01L29/417

CPC分类号： H01L29/401 ,  H01L21/28185 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

摘要： A method for manufacturing a semiconductor structure and a semiconductor device manufactured using the same are disclosed. In replacement gate process, the present invention is capable of reducing contact resistance at source/drain regions through forming doped amorphous Si layers above source/drain regions, forming contact holes (310) penetrating through the interlayer dielectric layer (300) and amorphous Si layers (251); wherein the contact holes (310) at least expose part of the source/drain regions (110), and contact layers are formed at the exposed area of the source/drain regions and sidewalls of the contact holes in the amorphous Si layer. Since contact layers are formed after high-k dielectric layer has been annealed, metal silicide layers are protected from damages at high temperatures.

摘要翻译： 公开了一种用于制造半导体结构的方法和使用其制造的半导体器件。 在替代栅极工艺中，本发明能够通过在源极/漏极区域之上形成掺杂的非晶Si层来形成源极/漏极区域的接触电阻，形成穿过层间介质层（300）的接触孔（310）和非晶Si层 （251）; 其中所述接触孔（310）至少暴露所述源极/漏极区域（110）的部分以及所述接触层在所述非晶硅层中的所述源极/漏极区域和所述接触孔的侧壁的暴露区域处形成。 由于在高k电介质层退火之后形成接触层，因此金属硅化物层在高温下被保护免受损坏。

公开(公告)号：US20130130448A1

公开(公告)日：2013-05-23

申请号：US13502788

申请日：2012-02-28

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： H01L21/8238

CPC分类号： H01L29/511 ,  H01L21/02057 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

摘要： The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.

摘要翻译： 本发明提供了一种用于形成和控制分子水平SiO 2界面层的方法，主要包括：在生长SiO 2界面层之前进行清洗，生长分子级超薄SiO 2界面层; 并控制高K栅极电介质和SiO 2界面层之间的反应，以进一步降低SiO 2界面层。 本公开可以严格地防止过程整合期间的氧侵入。 本公开可以获得具有小EOT的优质高K电介质膜。 制造过程简单易于集成。 它还兼容平面CMOS工艺，可以满足45纳米以下节点的高性能纳米级CMOS金属栅极/高K器件的要求。

公开(公告)号：US20130005097A1

公开(公告)日：2013-01-03

申请号：US13379169

申请日：2011-08-02

申请人： Gaobo Xu ,  Qiuxia Xu

发明人： Gaobo Xu ,  Qiuxia Xu

IPC分类号： H01L21/8238 ,  H01L21/336 ,  B82Y40/00

CPC分类号： H01L29/66545 ,  H01L21/823842

摘要： A method for integrating a replacement gate in a semiconductor device is disclosed. The method may comprise: forming a well region on a semiconductor substrate, and defining a N-type device region and/or a P-type device region; forming a sacrificial gate stack or sacrificial gate stacks respectively on the N-type device region and/or the P-type device region, the sacrificial gate stack or each of the sacrificial gate stacks comprising a sacrificial gate dielectric layer and a sacrificial gate electrode layer, wherein the sacrificial gate dielectric layer is disposed on the semiconductor substrate, and the sacrificial gate electrode layer is disposed on the sacrificial gate dielectric layer; forming a spacer or spacers surrounding the sacrificial gate stack or the respective sacrificial gate stacks; forming source/drain regions on both sides of the sacrificial gate stack or the respective sacrificial gate stacks and embedded into the semiconductor substrate; forming a SiO2 layer on the semiconductor substrate; forming a SOG layer on the SiO2 layer; etching the SOG layer until the SiO2 layer is exposed; etching the SOG layer and the SiO2 layer at different rates in such a manner that the SiO2 layer is planarized; and forming a N-type replacement gate stack on the N-type device region and/or a P-type replacement gate stack on the P-type device region, respectively.

摘要翻译： 公开了一种在半导体器件中集成置换栅极的方法。 该方法可以包括：在半导体衬底上形成阱区，并且限定N型器件区和/或P型器件区; 在N型器件区域和/或P型器件区域上分别形成牺牲栅极堆叠或牺牲栅极堆叠，牺牲栅极堆叠或每个牺牲栅极堆叠包括牺牲栅极电介质层和牺牲栅极电极层 其中所述牺牲栅极电介质层设置在所述半导体衬底上，并且所述牺牲栅极电极层设置在所述牺牲栅极电介质层上; 形成围绕所述牺牲栅极叠层或相应的牺牲栅极叠层的间隔物或间隔物; 在牺牲栅极堆叠或相应的牺牲栅极堆叠的两侧上形成源极/漏极区域并嵌入到半导体衬底中; 在所述半导体衬底上形成SiO 2层; 在SiO 2层上形成SOG层; 蚀刻SOG层直到暴露SiO 2层; 以使SiO 2层平坦化的方式以不同的速率蚀刻SOG层和SiO 2层; 以及分别在P型器件区域上的N型器件区域和/或P型替换栅极堆叠上形成N型替换栅极堆叠。

公开(公告)号：US20110256701A1

公开(公告)日：2011-10-20

申请号：US12990735

申请日：2010-06-28

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/32136 ,  H01L21/3215 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

摘要： The present application discloses a method for tuning the work function of a metal gate of the PMOS device, comprising the steps of depositing a layer of metal nitride or a metal on a layer of high-k gate dielectric by physical vapor deposition (PVD), as a metal gate; doping the metal gate with dopants such as Al, Pt, Ru, Ga, Ir by ion implantation; and driving the doped metal ions to the interface between the high-k gate dielectric and interfacial SiO2 by high-temperature annealing so that the doped metal ions accumulate at the interface or generate dipoles by interfacial reaction, which in turn tunes the work function of the metal gate. The inventive method can be widely used and its process is simple and convenient, has a better ability of tuning the work function of the metal gate, and is compatible with the conventional CMOS process.

摘要翻译： 本申请公开了一种用于调谐PMOS器件的金属栅极的功函数的方法，包括以下步骤：通过物理气相沉积（PVD）将金属氮化物或金属层沉积在高k栅极电介质层上， 作为金属门; 通过离子注入对诸如Al，Pt，Ru，Ga，Ir的掺杂剂掺杂金属栅; 并通过高温退火将掺杂的金属离子驱动到高k栅极电介质和界面SiO 2之间的界面，使得掺杂的金属离子在界面处积累或通过界面反应产生偶极子，这进而调节了 金属门。 本发明的方法可以广泛使用，其工艺简单方便，具有更好的调谐金属栅极功能的能力，并且与传统的CMOS工艺兼容。

公开(公告)号：US08748250B2

公开(公告)日：2014-06-10

申请号：US13129743

申请日：2011-02-21

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or oxynitride layer by rapid thermal oxidation; forming a high-k gate dielectric layer on the ultra-thin interfacial oxide layer by physical vapor deposition; performing a rapid thermal annealing after the deposition of the high-k; depositing a metal nitride gate by physical vapor deposition; doping the metal nitride gate by ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device, with a photoresist layer as a mask; depositing a polysilicon layer and a hard mask by a low pressure CVD process, and then performing photolithography process and etching the hard mask; removing the photoresist, and then etching the polysilicon layer/the metal gate/the high-k dielectric layer sequentially to provide a metal gate stack; forming a first spacer, and performing ion implantation with a low energy and a large angle for source/drain extensions; forming a second spacer, and performing ion implantation for source/drain regions; performing a thermal annealing so as to adjust of the metal gate work functions for the NMOS and PMOS devices, respectively, in the course when the dopants in the source/drain regions are activated.

摘要翻译： 本发明提供了一种用于将双金属栅极和双栅极电介质集成到CMOS器件中的方法，包括：通过快速热氧化生长超薄界面氧化物层或氧氮化物层; 通过物理气相沉积在超薄界面氧化物层上形成高k栅介质层; 在沉积高k后进行快速热退火; 通过物理气相沉积沉积金属氮化物栅极; 通过用于PMOS器件的P型掺杂剂和用于NMOS器件的N型掺杂剂通过离子注入来掺杂金属氮化物栅极，其中光致抗蚀剂层作为掩模; 通过低压CVD工艺沉积多晶硅层和硬掩模，然后进行光刻工艺并蚀刻硬掩模; 去除光致抗蚀剂，然后依次蚀刻多晶硅层/金属栅极/高k电介质层以提供金属栅极叠层; 形成第一间隔物，并以低能量和大角度对源/漏延伸进行离子注入; 形成第二间隔物，并对源/漏区进行离子注入; 在源极/漏极区域中的掺杂剂被激活的过程中，分别进行热退火以调整用于NMOS和PMOS器件的金属栅极功函数。

公开(公告)号：US20140154853A1

公开(公告)日：2014-06-05

申请号：US13878046

申请日：2012-12-07

申请人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu

发明人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu

IPC分类号： H01L29/66

CPC分类号： H01L21/28176 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

摘要翻译： 本公开公开了一种用于制造N型MOSFET的方法，包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的部分包括半导体衬底中的源极/漏极区，源/ 在半导体衬底之上的漏极区域和围绕替换栅极堆叠的栅极间隔; 去除MOSFET的替换栅极堆叠以形成暴露半导体衬底的表面的栅极开口; 在所述半导体的暴露表面上形成界面氧化物层; 在栅极开口中的界面氧化物层上形成高K栅极电介质层; 在高K栅极电介质层上形成第一金属栅极层; 将掺杂剂离子注入到第一金属栅极层中; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚，并且还 通过界面反应在高K栅极介电层和界面氧化物层之间的下界面产生电偶极子。

公开(公告)号：US20130078773A1

公开(公告)日：2013-03-28

申请号：US13576658

申请日：2011-11-22

申请人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

发明人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

IPC分类号： H01L21/8238

CPC分类号： H01L21/8238 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.

公开(公告)号：US20120115087A1

公开(公告)日：2012-05-10

申请号：US13123070

申请日：2011-02-15

申请人： Qiuxia Xu ,  Gaobo Xu

发明人： Qiuxia Xu ,  Gaobo Xu

IPC分类号： G03F7/20

CPC分类号： G03F7/0035 ,  G03F7/2039 ,  G03F7/405

摘要： A method for improving the efficiency of the electron-beam exposure is provided, comprising: step 1) coating a positive photoresist on a wafer to be processed, and performing a pre-baking; step 2) separating pattern data, optically exposing a group of relatively large patterns, and then performing a post-baking; step 3) developing the positive photoresist; step 4) performing a plasma fluorination; step 5) performing a baking to solidify the photoresist; step 6) coating a negative electron-beam resist and performing a pre-baking; step 7) electron-beam exposing a group of fine patterns; step 8) performing a post-baking; and step 9) developing the negative electron-beam resist, so that the fabrication of the patterns is finished. According to the invention, it is possible to save 30-60% of the exposure time. Thus, the exposure efficiency is significantly improved, and the cost is greatly reduced. Further, the method is totally compatible with the CMOS processes, without the need of any special equipments.

摘要翻译： 提供了一种提高电子束曝光效率的方法，包括：步骤1）在正在加工的晶片上涂覆正性光致抗蚀剂，并进行预烘烤; 步骤2）分离图案数据，光学地暴露一组相对大的图案，然后进行后烘烤; 步骤3）显影正性光致抗蚀剂; 步骤4）进行等离子体氟化; 步骤5）进行烘烤以固化光致抗蚀剂; 步骤6）涂覆负电子束抗蚀剂并进行预烘烤; 步骤7）电子束暴露一组精细图案; 步骤8）进行后烘烤; 和步骤9）显影负电子束抗蚀剂，使得图案的制​​造完成。 根据本发明，可以节省30-60％的曝光时间。 因此，曝光效率显着提高，成本大大降低。 此外，该方法与CMOS工艺完全兼容，无需任何特殊设备。

公开(公告)号：US20150170974A1

公开(公告)日：2015-06-18

申请号：US14355919

申请日：2012-12-07

申请人： Qiuxia Xu ,  Huilong Zhu ,  Gaobo Xu ,  Huajie Zhou ,  Dapeng Chen

发明人： Qiuxia Xu ,  Huilong Zhu ,  Gaobo Xu ,  Huajie Zhou ,  Dapeng Chen

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/324 ,  H01L29/167 ,  H01L21/266 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02

CPC分类号： H01L21/823857 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/266 ,  H01L21/28141 ,  H01L21/28176 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/823842 ,  H01L29/167 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse and accumulate at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide layer, and electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric and the interfacial oxide layer.

摘要翻译： 一种制造半导体器件的方法，包括：在所述半导体衬底上限定有源区; 在所述半导体衬底的表面上形成界面氧化物层; 在界面氧化物层上形成高K栅电介质; 在高K栅极电介质上形成第一金属栅极层; 在所述第一金属栅极层上形成伪栅极层; 图案化虚拟栅极层，第一金属栅极层，高K栅极电介质和界面氧化物层以形成栅极堆叠结构; 形成围绕所述栅堆叠结构的栅极间隔; 分别形成NMOS和PMOS的S / D区域; 通过CMP沉积层间电介质和平面化以暴露虚拟栅极层的表面; 去除虚拟栅极层以形成栅极开口; 将掺杂剂离子注入到第一金属栅极层中; 在所述第一金属栅极层上形成第二金属栅极层以填充所述栅极开口; 并执行退火，使得掺杂剂离子在高K栅极电介质和第一金属栅极层之间以及高K栅极电介质和界面氧化物层之间的下界面处的上界面处扩散并积聚，并且电偶极子 通过界面反应在高K栅极电介质和界面氧化物层之间的下界面产生。

公开(公告)号：US08530302B2

公开(公告)日：2013-09-10

申请号：US13576658

申请日：2011-11-22

申请人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

发明人： Qiuxia Xu ,  Yongliang Li ,  Gaobo Xu

IPC分类号： H01L21/8238 ,  H01L21/4763

CPC分类号： H01L21/8238 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.

摘要翻译： 制造CMOS FET的方法包括在形成常规介电隔离之后在半导体衬底上形成第一界面SiO 2层; 形成堆叠第一高K栅极电介质/第一金属栅极; 沉积第一个硬掩模; 通过光刻和蚀刻图案化第一硬掩模; 蚀刻未被第一硬掩模覆盖的第一金属栅极和第一高K栅极电介质的部分。 然后形成第二界面SiO 2层和第二高K栅极电介质/第二金属栅极的叠层; 通过光刻和蚀刻沉积和图案化第二个硬掩模; 蚀刻未被第二硬掩模覆盖的第二金属栅极和第二高K栅极电介质的部分以露出第一金属栅极上的第一硬掩模。 通过蚀刻去除第一硬掩模和第二硬掩模; 通过光刻和蚀刻沉积多晶硅层和第三硬掩模并图案化以形成栅叠层; 沉积和蚀刻电介质层以形成第一间隔物。 然后通过常规工艺形成源极/漏极区及其延伸，并且通过硅化物形成硅化物以提供接触和金属化。