公开(公告)号：US20050010897A1

公开(公告)日：2005-01-13

申请号：US10880523

申请日：2004-07-01

申请人： Hajime Ogawa ,  Taketo Heishi ,  Shuichi Takayama ,  Chen Zhao

发明人： Hajime Ogawa ,  Taketo Heishi ,  Shuichi Takayama ,  Chen Zhao

IPC分类号： G06F11/28 ,  G06F9/44

CPC分类号： G06F8/30 ,  G06F8/43 ,  G06F8/51

摘要： A test program generating apparatus for a compiler comprising: a conditional expression generating unit operable to receive a description of a control structure of a program and generate a plurality of conditional expressions to be inserted into insert parts of the conditional expressions of the control structure using a linear programming method, the plurality of conditional expressions allowing a control flow of the program to pass through all paths in the control structure; an initial value generating unit operable to generate initial values of variables, for each of all the paths, which are included in the plurality of conditional expressions for allowing the control flow of the program to pass through all the paths in the control structure; and a test program generating unit operable to generate a test program based on the control structure, the conditional expressions and the initial values.

摘要翻译： 一种用于编译器的测试程序生成装置，包括：条件表达式生成单元，用于接收对程序的控制结构的描述，并生成多个条件表达式，以使用以下操作插入到控制结构的条件表达式的插入部分中 所述多个条件表达式允许所述程序的控制流程通过所述控制结构中的所有路径; 初始值生成单元，用于针对包含在所述多个条件表达式中的每个所述路径生成用于允许所述程序的控制流通过所述控制结构中的所有路径的变量的初始值; 以及测试程序生成单元，其可操作以基于所述控制结构，所述条件表达式和所述初始值生成测试程序。

公开(公告)号：US20050010898A1

公开(公告)日：2005-01-13

申请号：US10880529

申请日：2004-07-01

申请人： Hajime Ogawa ,  Shuichi Takayama ,  Taketo Heishi ,  Chen Zhao

发明人： Hajime Ogawa ,  Shuichi Takayama ,  Taketo Heishi ,  Chen Zhao

IPC分类号： G06F11/28 ,  G06F9/44

CPC分类号： G06F8/30 ,  G06F8/51

摘要： A program generation apparatus according to the present invention includes a translation unit and a generation unit. The translation unit accepts a single HLSL (high level scripting language) script that defines a variety of program structures for programs to be generated, and translates the HLSL script into a plurality of MLSL (middle level scripting language) scripts, each of which describes one of the plurality of program structures defined by the HLSL script, which are different from each other. The generation unit generates programs that respectively correspond to the plurality of MLSL scripts.

摘要翻译： 根据本发明的程序生成装置包括翻译单元和生成单元。 翻译单元接受单个HLSL（高级脚本语言）脚本，定义要生成的程序的各种程序结构，并将HLSL脚本转换为多个MLSL（中级脚本语言）脚本，每个脚本描述一个 由HLSL脚本定义的多个程序结构彼此不同。 生成单元生成分别对应于多个MLSL脚本的程序。

公开(公告)号：US07185324B2

公开(公告)日：2007-02-27

申请号：US10631960

申请日：2003-08-01

申请人： Shohei Michimoto ,  Hajime Ogawa ,  Toshiyuki Sakata ,  Taketo Heishi ,  Shuichi Takayama

发明人： Shohei Michimoto ,  Hajime Ogawa ,  Toshiyuki Sakata ,  Taketo Heishi ,  Shuichi Takayama

IPC分类号： G06F9/45 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F9/5016 ,  G06F8/443 ,  G06F9/44557

摘要： Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n≦2m). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and excludes the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding specified data items are judged to be allocatable to the memory area.

摘要翻译： 公开了一种编译装置，用于生成由指令集构成的指令代码，每个指令集包括指定指示存储区中的数据项的位置的m位立即值的指令。 编译装置根据一个数据属性从由多个数据项组成的组X中依次选择数据项; 并且每当选择数据项时，判断所选择的数据项是否可分配给n字节存储区（n <= 2 ^{m）。 当判断为否定时，编译装置根据不同的数据属性指定所有选择的数据项中的数据项，并从组X中排除指定的数据项，并重复选择，直到剩余的所有数据项 在排除指定数据项之后的组X被判断为可分配给存储区。}

公开(公告)号：US06880150B1

公开(公告)日：2005-04-12

申请号：US09301284

申请日：1999-04-28

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a〜409c解码分支指令时，分支指令中包含的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US07823142B2

公开(公告)日：2010-10-26

申请号：US11245357

申请日：2005-10-07

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/45

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a至409c解码分支指令时，分支指令中包括的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US07698696B2

公开(公告)日：2010-04-13

申请号：US10608040

申请日：2003-06-30

申请人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

发明人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/443

摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

摘要翻译： 编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元， 根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理 指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

公开(公告)号：US07254807B2

公开(公告)日：2007-08-07

申请号：US10315877

申请日：2002-12-10

申请人： Toshiyuki Sakata ,  Taketo Heishi ,  Hajime Ogawa ,  Shohei Michimoto ,  Shuichi Takayama

发明人： Toshiyuki Sakata ,  Taketo Heishi ,  Hajime Ogawa ,  Shohei Michimoto ,  Shuichi Takayama

IPC分类号： G06F9/45

CPC分类号： G06F8/41 ,  G06F9/44521 ,  G06F9/44542

摘要： A compiling unit (110) generates indefinite branch information showing that an instruction set to be selected is indefinite, instead of generating a branch instruction. A linking unit (130) generates an appropriate direct addressing branch instruction by judging whether an instruction set used at a branch source and an instruction set used at a branch destination are the same. Also, one reference instruction set is determined. The compiling unit (110) adds a mode adjusting instruction that belongs to the reference instruction set and that is for causing a branch to an instruction placed at a branch destination and for selecting the instruction set that is originally to be selected. The mode adjusting instruction provides an alternative branch destination corresponding to an original branch destination, and the compiling unit (110) generates an indirect addressing branch instruction for causing a branch to the alternative branch destination and for selecting the reference instruction set.

摘要翻译： 编译单元（110）产生不确定的分支信息，表示选择的指令集是不确定的，而不是生成分支指令。 链接单元（130）通过判断在分支源使用的指令集和在分支目的地使用的指令集是否相同来生成适当的直接寻址分支指令。 此外，确定一个参考指令集。 编译单元（110）添加属于参考指令集的模式调整指令，其用于使分支到位于分支目的地的指令，并且用于选择最初被选择的指令集。 模式调整指令提供与原始分支目的地相对应的替代分支目的地，并且编译单元（110）生成用于使分支到备选分支目的地并用于选择参考指令集的间接寻址分支指令。

公开(公告)号：US20080141229A1

公开(公告)日：2008-06-12

申请号：US11969083

申请日：2008-01-03

申请人： Taketo Heishi ,  Hajime Ogawa ,  Shuichi Takayama ,  Toshiyuki Sakata ,  Shohei Michimoto

发明人： Taketo Heishi ,  Hajime Ogawa ,  Shuichi Takayama ,  Toshiyuki Sakata ,  Shohei Michimoto

IPC分类号： G06F9/45 ,  G06F9/312

CPC分类号： G06F9/30094 ,  G06F9/30021 ,  G06F9/30072

摘要： The first, second, and third operating units 441 to 443 each perform a predetermined operation according to an instruction before a point of time partway through a clock cycle. When having performed a comparison operation, each operating unit outputs a result value to the condition flag operating unit 51. The condition flag operating unit 51 calculates a new condition flag value by performing a logical operation on either (a) a value that has been read from the condition flag register 46 and the result value or (b) the result values themselves. The condition flag operating unit 51 outputs, before the clock cycle ends, the new condition flag value to one of the first, second, and third gates 451 to 453 that is related to a conditional instruction so as to control nullification of the conditional new condition flag value.

摘要翻译： 第一，第二和第三操作单元441至443各自根据在时钟周期的中途的时间点之前的指令执行预定的操作。 当执行比较操作时，每个操作单元将结果值输出到条件标志操作单元51。 条件标志操作单元51通过对（a）从条件标志寄存器46读取的值和结果值或（b）结果值本身执行逻辑运算来计算新条件标志值。 条件标志操作单元51在时钟周期结束之前将新条件标志值输出到与条件指令相关的第一，第二和第三门451至453中的一个，以便控制条件新条件的无效 标志值。

公开(公告)号：US07076638B2

公开(公告)日：2006-07-11

申请号：US10246482

申请日：2002-09-19

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

公开(公告)号：US07073169B2

公开(公告)日：2006-07-04

申请号：US10174108

申请日：2002-06-17

申请人： Hajime Ogawa ,  Shuichi Takayama ,  Taketo Heishi ,  Nobuo Higaki

发明人： Hajime Ogawa ,  Shuichi Takayama ,  Taketo Heishi ,  Nobuo Higaki

IPC分类号： G06F9/45

CPC分类号： G06F8/4441

摘要： A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section. Thus, a compiler device employing conditional executable instructions is provided that is capable of generating an assembler code that does not degrade the performance when the instructions are executed, even if a source program includes a branch instruction that causes a then part and an else part to be executed through unbalanced numbers of cycles, respectively.

摘要翻译： 编译器装置包括条件可执行指令生成单元和分支指令插入单元。 条件可执行指令生成单元生成当满足条件可执行指令引用的条件时执行的条件可执行指令。 在存在包含在一个周期或多个周期中不执行指令的非执行条件的部分的情况下，分支指令插入单元插入参考非执行条件的条件分支指令，并且 指示在该部分的最后一个周期之后立即分支到一个周期，直到在该部分开始之前的一个周期的指令之后。 因此，提供了一种使用条件可执行指令的编译器装置，其能够生成当执行指令时不降低性能的汇编代码，即使源程序包括分支指令，该分支指令导致随后的部分和其他部分 分别通过不平衡的周期数执行。