公开(公告)号：US5905875A

公开(公告)日：1999-05-18

申请号：US592512

申请日：1996-01-26

申请人： Hajime Takahashi ,  Nobuhisa Hattori ,  Toshihide Tsuzuki ,  Jun Funaki

发明人： Hajime Takahashi ,  Nobuhisa Hattori ,  Toshihide Tsuzuki ,  Jun Funaki

IPC分类号： G06F11/18 ,  G06F11/20 ,  G06F13/36 ,  G06F15/16 ,  G06F15/173 ,  G06F13/00

CPC分类号： G06F11/2007

摘要： A multiprocessor system having the capability of increasing the speed of a bus clock while retaining high reliability and fault tolerant performance as well as utilizing the current operating system resources. The multiprocessor system is made up of a plurality of processor modules connected together through a duplicated system bus. The duplicated system bus is divided into a plurality of segments, and these segments are coupled together by at least one bus extender mechanism. The multiprocessor system is also provided with first notification means which is provided between bus control mechanisms for controlling the states of physical buses and the bus extender mechanism, and the bus control mechanisms and the bus extender mechanism are mutually notified of the state of each mechanism through the first notification means.

摘要翻译： 具有提高总线时钟速度同时保持高可靠性和容错性能以及利用当前操作系统资源的能力的多处理器系统。 多处理器系统由通过复制的系统总线连接在一起的多个处理器模块组成。 复制的系统总线被分成多个段，并且这些段通过至少一个总线扩展器机制耦合在一起。 多处理器系统还设置有第一通知装置，其设置在用于控制物理总线的状态的总线控制机构和总线扩展器机构之间，并且总线控制机构和总线扩展器机制通过每个机制的状态相互通知 第一通知手段。

公开(公告)号：US08339162B2

公开(公告)日：2012-12-25

申请号：US12770030

申请日：2010-04-29

申请人： Toshihide Tsuzuki ,  Hirotoshi Inoue

发明人： Toshihide Tsuzuki ,  Hirotoshi Inoue

IPC分类号： H03B1/00

CPC分类号： H03K19/0005 ,  H03K19/018592

摘要： A circuit device has a first output buffer including a first adjustment circuit for adjusting a level of the first output signal, a first input buffer connected to the first output buffer, an adjustment controller for outputting a test signal to the first output buffer, outputting a control signal to the first adjustment circuit so that the level of the first output signal is adjusted on the basis of the control signal, monitoring an output of the first input buffer, and adjusting the control signal on the basis of the monitoring the output of the first input buffer, a second output buffer connected to the adjustment controller and operable to assume either an active or a non-active state, for outputting a second output signal when controlled to assume an active state, including a second adjustment circuit, and a second input buffer.

摘要翻译： 电路装置具有第一输出缓冲器，包括用于调节第一输出信号的电平的第一调节电路，连接到第一输出缓冲器的第一输入缓冲器，用于向第一输出缓冲器输出测试信号的调整控制器， 控制信号到第一调整电路，使得基于控制信号调整第一输出信号的电平，监视第一输入缓冲器的输出，并且基于监视第一输入信号的输出来调整控制信号 第一输入缓冲器，连接到调节控制器的第二输出缓冲器，并且可操作以呈现有源或非有效状态，用于当被控制为呈现包括第二调整电路的有效状态时输出第二输出信号，以及第二输入缓冲器 输入缓冲区。

公开(公告)号：US20060204156A1

公开(公告)日：2006-09-14

申请号：US11370035

申请日：2006-03-08

申请人： Tetsu Takehara ,  Natsuki Sensui ,  Hironari Sakoda ,  Nobuyuki Hagiwara ,  Taketoshi Chifu ,  Shingo Nagoshi ,  Toshihide Tsuzuki

发明人： Tetsu Takehara ,  Natsuki Sensui ,  Hironari Sakoda ,  Nobuyuki Hagiwara ,  Taketoshi Chifu ,  Shingo Nagoshi ,  Toshihide Tsuzuki

IPC分类号： F16C41/04 ,  F16C13/00 ,  F16C32/00

CPC分类号： F16C43/04 ,  B60B27/00 ,  F16C19/185 ,  F16C19/386 ,  F16C33/60 ,  F16C35/063 ,  F16C41/007 ,  F16C2326/02 ,  G01P3/443 ,  G01P3/446 ,  G01P3/488

摘要： A construction is adopted in which an annular spacer 27 is held between first and second inner races 2a, 2b. An internal clearance in a double-row bearing unit is measured in a middle step of assembling work of a wheel supporting bearing assembly, and in the event that a resultant measured value does not become a proper value, an axial dimension of the spacer 27 is adjusted, so that the internal clearance becomes the proper value. Thereafter, the assembling work is made to continue until the assembling work is completed. A problem which is to be solved by the invention is solved in the way described above.

摘要翻译： 采用其中环形间隔件27保持在第一和第二内圈2a，2b之间的结构。 双列轴承单元的内部间隙在车轮支承轴承组件的组装工作的中间步骤中被测量，并且在结果测量值不成为适当值的情况下，间隔件27的轴向尺寸为 调节，使内部间隙成为适当的值。 此后，进行组装工作，直到组装工作完成。 本发明要解决的问题以上述方式解决。

公开(公告)号：US06414609B1

公开(公告)日：2002-07-02

申请号：US09948770

申请日：2001-09-10

申请人： Makoto Zukawa ,  Toshihide Tsuzuki

发明人： Makoto Zukawa ,  Toshihide Tsuzuki

IPC分类号： H03M740

CPC分类号： G06F13/4018

摘要： A data width conversion apparatus has a buffer for storing output-incomplete partial data of input data received in the past and a block shifter for combining the output-incomplete partial data stored in said buffer with new input data. In the combined data by the block shifter, a portion of a fixed data width is outputted in form of an output data, and data less than the fixed data width or data exceeding the fixed data width is stored in the buffer so as to be combined with the successive input data.

摘要翻译： 数据宽度转换装置具有用于存储过去接收的输入数据的输出不完整部分数据的缓冲器和用于将存储在所述缓冲器中的输出不完全部分数据与新输入数据组合的块移位器。 在通过块移位器的组合数据中，以输出数据的形式输出固定数据宽度的一部分，并且小于固定数据宽度的数据或超过固定数据宽度的数据被存储在缓冲器中以便被组合 与连续的输入数据。