公开(公告)号：US07369113B2

公开(公告)日：2008-05-06

申请号：US11080848

申请日：2005-03-16

申请人： Hajime Washio ,  Shinya Takahashi ,  Yuhiehiroh Murakami ,  Seijirou Gyouten ,  Shigeto Yoshida

发明人： Hajime Washio ,  Shinya Takahashi ,  Yuhiehiroh Murakami ,  Seijirou Gyouten ,  Shigeto Yoshida

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2310/04

摘要： A driving device of a display device includes: a data signal line driving circuit including a shift register which has (i) multiple stages of flip-flops each of which operates in synchronism with a source clock signal and (ii) a level shifter for boosting the source clock signal whose amplitude is smaller than a driving voltage of each of the flip-flops so as to apply the driving voltage to the flip-flop, said data signal line driving circuit causing a sampling circuit to sample the image display data signal based on an output from the shift register so as to output the image display data signal to the data signal line; and control means for causing a frequency of the source clock signal in case of displaying an image to be higher than a frequency of the source clock signal in case of normal display in which multi-gradation display is performed in a full-color mode. Thus, it is possible to provide a driving device of a display device, a display device, and a driving method of the display device, whereby it is possible to reduce power consumption caused by an invalid current of the level shifter.

摘要翻译： 显示装置的驱动装置包括：数据信号线驱动电路，包括移位寄存器，其具有（i）多个触发器级，每个触发器与源时钟信号同步操作;以及（ii）用于升压的电平移位器 所述源时钟信号的振幅小于每个触发器的驱动电压，以将驱动电压施加到触发器，所述数据信号线驱动电路使采样电路基于图像显示数据信号进行采样 在移位寄存器的输出上输出图像显示数据信号至数据信号线; 以及控制装置，用于在以全色模式进行多灰度显示的正常显示的情况下，在显示图像的情况下使源时钟信号的频率高于源时钟信号的频率。 因此，可以提供显示装置的驱动装置，显示装置和显示装置的驱动方法，从而可以降低由电平转换器的无效电流引起的功耗。

公开(公告)号：US20050206604A1

公开(公告)日：2005-09-22

申请号：US11080848

申请日：2005-03-16

申请人： Hajime Washio ,  Shinya Takahashi ,  Yuhiehiroh Murakami ,  Seijirou Gyouten ,  Shigeto Yoshida

发明人： Hajime Washio ,  Shinya Takahashi ,  Yuhiehiroh Murakami ,  Seijirou Gyouten ,  Shigeto Yoshida

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2310/04

摘要： A driving device of a display device includes: a data signal line driving circuit including a shift register which has (i) multiple stages of flip-flops each of which operates in synchronism with a source clock signal and (ii) a level shifter for boosting the source clock signal whose amplitude is smaller than a driving voltage of each of the flip-flops so as to apply the driving voltage to the flip-flop, said data signal line driving circuit causing a sampling circuit to sample the image display data signal based on an output from the shift register so as to output the image display data signal to the data signal line; and control means for causing a frequency of the source clock signal in case of displaying an image to be higher than a frequency of the source clock signal in case of normal display in which multi-gradation display is performed in a full-color mode. Thus, it is possible to provide a driving device of a display device, a display device, and a driving method of the display device, whereby it is possible to reduce power consumption caused by an invalid current of the level shifter.

摘要翻译： 显示装置的驱动装置包括：数据信号线驱动电路，包括移位寄存器，其具有（i）多个触发器级，每个触发器与源时钟信号同步操作;以及（ii）用于升压的电平移位器 所述源时钟信号的振幅小于每个触发器的驱动电压，以将驱动电压施加到触发器，所述数据信号线驱动电路使采样电路基于图像显示数据信号进行采样 在移位寄存器的输出上输出图像显示数据信号到数据信号线; 以及控制装置，用于在以全色模式进行多灰度显示的正常显示的情况下，在显示图像的情况下使源时钟信号的频率高于源时钟信号的频率。 因此，可以提供显示装置的驱动装置，显示装置和显示装置的驱动方法，从而可以降低由电平转换器的无效电流引起的功耗。

公开(公告)号：US20050206637A1

公开(公告)日：2005-09-22

申请号：US11080849

申请日：2005-03-16

申请人： Shinya Takahashi ,  Hajime Washio ,  Yuhichiroh Murakami ,  Seijirou Gyouten

发明人： Shinya Takahashi ,  Hajime Washio ,  Yuhichiroh Murakami ,  Seijirou Gyouten

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0232 ,  G09G2310/04 ,  G09G2330/021

摘要： A driving device of a display device includes: a data signal line driving circuit, provided with a shift register having a level shifter for boosting a source clock signal so as to apply the source clock signal to a flip-flop, which causes a sampling circuit to directly sample a multi-gradation data signal based on each output from the shift register so as to output the multi-gradation data signal to each of a plurality of data signal lines; a control circuit for switching a full-screen display mode in which a whole of the display screen performs display and a partial-screen display mode in which only a part of the display screen performs time-sharing display; a data generating section for generating a constant voltage data writing signal made of a constant voltage; and a control circuit for outputting a selection signal for causing a nondisplay portion to directly sample the constant voltage data writing signal from the constant voltage data writing signal generation means so as to output the constant voltage data writing signal to a plurality of data signal lines. This makes it possible to provide a driving device of a display device, a display device, and a driving method of a display device, all of which make it possible to reduce power consumption in a waiting state.

摘要翻译： 显示装置的驱动装置包括：数据信号线驱动电路，其具有移位寄存器，该移位寄存器具有用于升压源时钟信号的电平移位器，以将源时钟信号施加到触发器，这导致采样电路 基于来自移位寄存器的每个输出直接采样多灰度数据信号，以将多灰度数据信号输出到多条数据信号线中的每一条; 用于切换整个显示屏幕执行显示的全屏显示模式的控制电路和仅显示屏幕的一部分执行分时显示的部分屏幕显示模式; 数据生成部，其生成由恒定电压构成的恒定电压数据写入信号; 以及控制电路，用于输出用于使非显示部分从恒定电压数据写入信号产生装置直接采样恒定电压数据写入信号的选择信号，以将恒定电压数据写入信号输出到多条数据信号线。 这使得可以提供显示装置的驱动装置，显示装置和显示装置的驱动方法，所有这些都可以在等待状态下降低功耗。

公开(公告)号：US07372445B2

公开(公告)日：2008-05-13

申请号：US11080849

申请日：2005-03-16

申请人： Shinya Takahashi ,  Hajime Washio ,  Yuhichiroh Murakami ,  Seijirou Gyouten

发明人： Shinya Takahashi ,  Hajime Washio ,  Yuhichiroh Murakami ,  Seijirou Gyouten

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0232 ,  G09G2310/04 ,  G09G2330/021

摘要： A driving device of a display device includes: a data signal line driving circuit, provided with a shift register having a level shifter for boosting a source clock signal so as to apply the source clock signal to a flip-flop, which causes a sampling circuit to directly sample a multi-gradation data signal based on each output from the shift register so as to output the multi-gradation data signal to each of a plurality of data signal lines; a control circuit for switching a full-screen display mode in which a whole of the display screen performs display and a partial-screen display mode in which only a part of the display screen performs time-sharing display; a data generating section for generating a constant voltage data writing signal made of a constant voltage; and a control circuit for outputting a selection signal for causing a nondisplay portion to directly sample the constant voltage data writing signal from the constant voltage data writing signal generation means so as to output the constant voltage data writing signal to a plurality of data signal lines. This makes it possible to provide a driving device of a display device, a display device, and a driving method of a display device, all of which make it possible to reduce power consumption in a waiting state.

摘要翻译： 显示装置的驱动装置包括：数据信号线驱动电路，其具有移位寄存器，该移位寄存器具有用于升压源时钟信号的电平移位器，以将源时钟信号施加到触发器，这导致采样电路 基于来自移位寄存器的每个输出直接采样多灰度数据信号，以将多灰度数据信号输出到多条数据信号线中的每一条; 用于切换整个显示屏幕执行显示的全屏显示模式的控制电路和仅显示屏幕的一部分执行分时显示的部分屏幕显示模式; 数据生成部，其生成由恒定电压构成的恒定电压数据写入信号; 以及控制电路，用于输出用于使非显示部分从恒定电压数据写入信号产生装置直接采样恒定电压数据写入信号的选择信号，以将恒定电压数据写入信号输出到多条数据信号线。 这使得可以提供显示装置的驱动装置，显示装置和显示装置的驱动方法，所有这些都可以在等待状态下降低功耗。

公开(公告)号：US07733321B2

公开(公告)日：2010-06-08

申请号：US11543219

申请日：2006-10-05

申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

摘要翻译： 移位寄存器包括多级触发器。 作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。 在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入 信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。 通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

公开(公告)号：US20090115716A1

公开(公告)日：2009-05-07

申请号：US11921116

申请日：2006-06-12

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Noboru Matsuda ,  Hajime Washio

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Noboru Matsuda ,  Hajime Washio

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0232 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2340/0442 ,  G11C19/28

摘要： In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.

摘要翻译： 在本发明的一个实施例中，本移位寄存器是设置在显示设备中的移位寄存器，通过该移位寄存器可以获得部分屏幕显示。 移位寄存器包括设置在中间级中的移位停止电路，并且在部分屏幕显示中停止移位寄存器的第一级和最后级之间的移位寄存器的操作。 移位寄存器还包括一个电路，其被提供在除了中间级之外的阶段中，使得该电路不执行信号处理而用作信号路径。 该电路与配置中的换挡停止电路相同。 上述可以改善采用本移位寄存器的显示装置的显示质量。

公开(公告)号：US20070242021A1

公开(公告)日：2007-10-18

申请号：US11812461

申请日：2007-06-19

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

IPC分类号： H03K19/0175

CPC分类号： G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

公开(公告)号：US08248348B2

公开(公告)日：2012-08-21

申请号：US11812461

申请日：2007-06-19

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

IPC分类号： H03K19/0175 ,  H03L5/00 ,  G09G5/00 ,  G09G3/28 ,  G09G3/36

CPC分类号： G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

摘要翻译： 电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。 电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器 输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。 利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。

公开(公告)号：US08174479B2

公开(公告)日：2012-05-08

申请号：US11921116

申请日：2006-06-12

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Noboru Matsuda ,  Hajime Washio

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Noboru Matsuda ,  Hajime Washio

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0232 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2340/0442 ,  G11C19/28

摘要： In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.

摘要翻译： 在本发明的一个实施例中，本移位寄存器是设置在显示设备中的移位寄存器，通过该移位寄存器可以获得部分屏幕显示。 移位寄存器包括设置在中间级中的移位停止电路，并且在部分屏幕显示中停止移位寄存器的第一级和最后级之间的移位寄存器的操作。 移位寄存器还包括一个电路，其被提供在除了中间级之外的阶段中，使得该电路不执行信号处理而用作信号路径。 该电路与配置中的换挡停止电路相同。 上述可以改善采用本移位寄存器的显示装置的显示质量。

公开(公告)号：US07289097B2

公开(公告)日：2007-10-30

申请号：US10702077

申请日：2003-11-06

申请人： Seijirou Gyouten ,  Sachio Tsujino ,  Hajime Washio ,  Eiji Matsuda ,  Keiichi Ina ,  Yuhichiroh Murakami ,  Shunsuke Hayashi ,  Mamoru Onda

发明人： Seijirou Gyouten ,  Sachio Tsujino ,  Hajime Washio ,  Eiji Matsuda ,  Keiichi Ina ,  Yuhichiroh Murakami ,  Shunsuke Hayashi ,  Mamoru Onda

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0289 ,  G11C19/00 ,  G11C19/28

摘要： The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.

摘要翻译： 本发明公开了一种扫描方向控制电路，其包括双向移位寄存器，其中根据切换信号L / R切换移位方向，当切换信号L / R在比驱动电压低的振幅时由电平移位器升压。 扫描方向控制电路包括电平移位器和双向移位寄存器之间的锁存电路，并且控制电路使得锁存电路在构成双向移位寄存器的触发器的移位操作之后响应于输出而完成锁存操作 触发器的信号。 控制电路在锁存定时之前，之后和之后的时段中使电平移位器进入有效状态，并且在剩余时间段内使电平移位器进入非活动状态。 利用这种布置，可以在低功耗的情况下以预定的时序提供开关信号L / R，而不管其外部输入定时。