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1.发明授权Driving device of display device, display device and driving method of display device 有权显示装置的驱动装置，显示装置和显示装置的驱动方法公开(公告)号：US07369113B2
公开(公告)日：2008-05-06
申请号：US11080848
申请日：2005-03-16
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2310/0289 , G09G2310/04
摘要： A driving device of a display device includes: a data signal line driving circuit including a shift register which has (i) multiple stages of flip-flops each of which operates in synchronism with a source clock signal and (ii) a level shifter for boosting the source clock signal whose amplitude is smaller than a driving voltage of each of the flip-flops so as to apply the driving voltage to the flip-flop, said data signal line driving circuit causing a sampling circuit to sample the image display data signal based on an output from the shift register so as to output the image display data signal to the data signal line; and control means for causing a frequency of the source clock signal in case of displaying an image to be higher than a frequency of the source clock signal in case of normal display in which multi-gradation display is performed in a full-color mode. Thus, it is possible to provide a driving device of a display device, a display device, and a driving method of the display device, whereby it is possible to reduce power consumption caused by an invalid current of the level shifter.
摘要翻译： 显示装置的驱动装置包括：数据信号线驱动电路，包括移位寄存器，其具有（i）多个触发器级，每个触发器与源时钟信号同步操作;以及（ii）用于升压的电平移位器 所述源时钟信号的振幅小于每个触发器的驱动电压，以将驱动电压施加到触发器，所述数据信号线驱动电路使采样电路基于图像显示数据信号进行采样 在移位寄存器的输出上输出图像显示数据信号至数据信号线; 以及控制装置，用于在以全色模式进行多灰度显示的正常显示的情况下，在显示图像的情况下使源时钟信号的频率高于源时钟信号的频率。 因此，可以提供显示装置的驱动装置，显示装置和显示装置的驱动方法，从而可以降低由电平转换器的无效电流引起的功耗。
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2.发明申请Driving device of display device, display device and driving method of display device 有权显示装置的驱动装置，显示装置和显示装置的驱动方法公开(公告)号：US20050206604A1
公开(公告)日：2005-09-22
申请号：US11080848
申请日：2005-03-16
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2310/0289 , G09G2310/04
摘要： A driving device of a display device includes: a data signal line driving circuit including a shift register which has (i) multiple stages of flip-flops each of which operates in synchronism with a source clock signal and (ii) a level shifter for boosting the source clock signal whose amplitude is smaller than a driving voltage of each of the flip-flops so as to apply the driving voltage to the flip-flop, said data signal line driving circuit causing a sampling circuit to sample the image display data signal based on an output from the shift register so as to output the image display data signal to the data signal line; and control means for causing a frequency of the source clock signal in case of displaying an image to be higher than a frequency of the source clock signal in case of normal display in which multi-gradation display is performed in a full-color mode. Thus, it is possible to provide a driving device of a display device, a display device, and a driving method of the display device, whereby it is possible to reduce power consumption caused by an invalid current of the level shifter.
摘要翻译： 显示装置的驱动装置包括：数据信号线驱动电路，包括移位寄存器，其具有（i）多个触发器级，每个触发器与源时钟信号同步操作;以及（ii）用于升压的电平移位器 所述源时钟信号的振幅小于每个触发器的驱动电压，以将驱动电压施加到触发器，所述数据信号线驱动电路使采样电路基于图像显示数据信号进行采样 在移位寄存器的输出上输出图像显示数据信号到数据信号线; 以及控制装置，用于在以全色模式进行多灰度显示的正常显示的情况下，在显示图像的情况下使源时钟信号的频率高于源时钟信号的频率。 因此，可以提供显示装置的驱动装置，显示装置和显示装置的驱动方法，从而可以降低由电平转换器的无效电流引起的功耗。
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公开(公告)号：US20050140621A1
公开(公告)日：2005-06-30
申请号：US11060963
申请日：2005-02-18
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
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4.发明授权公开(公告)号：US07375708B2
公开(公告)日：2008-05-20
申请号：US10105652
申请日：2002-03-25
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/2051 , G09G3/3648 , G09G3/3688 , G09G2300/0408 , G09G2310/027 , G09G2310/0297
摘要： A data signal line drive circuit supplying a video signal to a pixel array performs pseudo tone gradation processing with respect to the video signal that is sent to an n number of data signal lines SL by m (
摘要翻译： 向像素阵列提供视频信号的数据信号线驱动电路相对于通过伪色调灰度处理的m（
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5.发明授权Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法公开(公告)号：US06879313B1
公开(公告)日：2005-04-12
申请号：US09523511
申请日：2000-03-10
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
摘要翻译： 移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路 线和多个锁存电路。 在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。 在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。
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公开(公告)号：US06873313B2
公开(公告)日：2005-03-29
申请号：US09822768
申请日：2001-03-30
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3614 , G09G3/3685 , G09G2310/0232 , G09G2310/0251 , G09G2330/021
摘要： An image display device of this invention includes a pre-charging voltage stabilizing section having current controlling means and charge holding means which respectively include a resistor and a capacitor to stabilize a pre-charging voltage. The charge holding means holds a voltage to be supplied to data signal lines, and the current controlling means suppresses a current flow from a control signal generating circuit, thereby suppressing power fluctuation at the control signal generating circuit. This suppresses fluctuation in the pre-charging voltage and enables data signal lines to be charged to a predetermined voltage, thereby suppressing deterioration of image quality and an increase in power consumption of the image display device. Further, when using the pre-charging voltage stabilizing section and setting a portion of a display as a video data non-display area avoiding display of video data in a non-match image display mode to display at fixed brightness in the video data non-display area by a pre-charging voltage from a pre-charging circuit, a control signal is suspended in a fixed period, thus realizing a non-match image display mode to display a video image of an aspect ratio different from that of a screen of a display without impairing an image quality, and saving power.
摘要翻译： 本发明的图像显示装置包括具有电流控制装置和电荷保持装置的预充电电压稳定部分，其分别包括用于稳定预充电电压的电阻器和电容器。 电荷保持装置保持要提供给数据信号线的电压，并且电流控制装置抑制来自控制信号发生电路的电流，从而抑制控制信号发生电路的功率波动。 这抑制了预充电电压的波动，并且能够使数据信号线被充电到预定电压，从而抑制图像质量的劣化和图像显示装置的功耗的增加。 此外，当使用预充电电压稳定部分并且将显示器的一部分设置为视频数据非显示区域时，避免以不匹配的图像显示模式显示视频数据，以在视频数据非显示区域中以固定亮度显示， 通过来自预充电电路的预充电电压来显示区域，控制信号以固定的时间段被暂停，从而实现不匹配的图像显示模式，以显示不同于屏幕的宽高比的视频图像 显示而不损害图像质量，并且节省电力。
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公开(公告)号：US07173598B2
公开(公告)日：2007-02-06
申请号：US11063718
申请日：2005-02-22
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
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8.发明授权Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法公开(公告)号：US07193604B2
公开(公告)日：2007-03-20
申请号：US11060963
申请日：2005-02-18
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
摘要翻译： 移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路 线和多个锁存电路。 在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。 在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。
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公开(公告)号：US07042431B1
公开(公告)日：2006-05-09
申请号：US09711009
申请日：2000-11-09
申请人： Hajime Washio , Nobuhiro Kuwabara , Shigeto Yoshida , Yuji Asoh , Hiroshi Yoneda
发明人： Hajime Washio , Nobuhiro Kuwabara , Shigeto Yoshida , Yuji Asoh , Hiroshi Yoneda
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3614 , G09G2310/0251 , G09G2320/0233
摘要： In a vertical retrace interval, a pre-charge potential or a signal potential is applied to each polarity for AC driving liquid crystal at least once each, so as to maintain fluctuations in pixel potential between the positive polarity side and the negative polarity side uniform, and minimum required potentials are supplied to the data signal line, thereby suppressing decrease in image quality without significantly increasing power consumption.
摘要翻译： 在垂直回扫间隔中，对交流驱动液晶的各极性施加预充电电位或信号电位至少一次，以保持正极侧和负极侧之间的像素电位的波动均匀， 并且将最小所需电位提供给数据信号线，从而在不显着增加功耗的情况下抑制图像质量的降低。
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10.发明申请公开(公告)号：US20050168252A1
公开(公告)日：2005-08-04
申请号：US11063718
申请日：2005-02-23
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
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