-
公开(公告)号：US08634227B2
公开(公告)日：2014-01-21
申请号：US13184795
申请日：2011-07-18
申请人： Hak Soo Yu , In Gyu Baek , Hong Sun Hwang , Su A Kim , Mu Jin Seo
发明人： Hak Soo Yu , In Gyu Baek , Hong Sun Hwang , Su A Kim , Mu Jin Seo
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/71
摘要： Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current.
摘要翻译： 提供了半导体电阻式存储器件。 电阻式存储器件包括多个单元电池。 单位单元的源极线和数据输入/输出线可以被选择性地连接以具有基本上相同的电压电平以用于在单位电池处于非活动状态或未选择状态时进行均衡。 均衡可能会降低电流消耗并保护写入错误，并保护漏电流。
-
公开(公告)号：US20120020142A1
公开(公告)日：2012-01-26
申请号：US13184795
申请日：2011-07-18
申请人： Hak Soo Yu , In Gyu Baek , Hong Sun Hwang , Su A. Kim , Mu Jin Seo
发明人： Hak Soo Yu , In Gyu Baek , Hong Sun Hwang , Su A. Kim , Mu Jin Seo
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/71
摘要： Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current.
摘要翻译： 提供了半导体电阻式存储器件。 电阻式存储器件包括多个单元电池。 单位单元的源极线和数据输入/输出线可以被选择性地连接以具有基本上相同的电压电平以用于在单位电池处于非活动状态或未选择状态时进行均衡。 均衡可能会降低电流消耗并保护写入错误，并保护漏电流。
-
3.发明申请RESISTIVE MEMORY DEVICES, INITIALIZATION METHODS, AND ELECTRONIC DEVICES INCORPORATING SAME 有权电阻记忆体装置，初始化方法和包含它们的电子装置公开(公告)号：US20120099364A1
公开(公告)日：2012-04-26
申请号：US13238669
申请日：2011-09-21
申请人： Chul Woo Park , In Gyu Baek , Dong Hyun Sohn , Hong Sun Hwang
发明人： Chul Woo Park , In Gyu Baek , Dong Hyun Sohn , Hong Sun Hwang
IPC分类号： G11C11/21
CPC分类号： G11C13/0069 , G11C13/00 , G11C2013/0083 , G11C2213/71 , G11C2213/79
摘要： A resistive memory device and method of initialization are provided. The resistive memory device includes a first group of resistive memory cells connected between bit lines and a first plate and a second group connected between bit lines and a second plate. First and second initialization voltages are respectively applied to the first and second plates outside a normal path associated with a normal operation of the resistive memory cells.
摘要翻译： 提供了电阻式存储器件和初始化方法。 电阻性存储器件包括连接在位线与第一板之间的第一组电阻存储器单元和连接在位线和第二板之间的第二组。 第一和第二初始化电压分别施加到与电阻存储器单元的正常操作相关联的正常路径之外的第一和第二板。
-
4.发明授权Resistive memory devices, initialization methods, and electronic devices incorporating same 有权电阻式存储器件，初始化方法和结合其的电子器件公开(公告)号：US08737112B2
公开(公告)日：2014-05-27
申请号：US13238669
申请日：2011-09-21
申请人： Chul Woo Park , In Gyu Baek , Dong Hyun Sohn , Hong Sun Hwang
发明人： Chul Woo Park , In Gyu Baek , Dong Hyun Sohn , Hong Sun Hwang
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/00 , G11C2013/0083 , G11C2213/71 , G11C2213/79
摘要： A resistive memory device and method of initialization are provided. The resistive memory device includes a first group of resistive memory cells connected between bit lines and a first plate and a second group connected between bit lines and a second plate. First and second initialization voltages are respectively applied to the first and second plates outside a normal path associated with a normal operation of the resistive memory cells.
摘要翻译： 提供了电阻式存储器件和初始化方法。 电阻性存储器件包括连接在位线与第一板之间的第一组电阻存储器单元和连接在位线和第二板之间的第二组。 第一和第二初始化电压分别施加到与电阻存储器单元的正常操作相关联的正常路径之外的第一和第二板。
-
-
-
搜索结果
4 条记录 (耗时 0.024 秒)
