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    Semiconductor memory device including vertical channel transistors
    3.
    发明授权
    Semiconductor memory device including vertical channel transistors 有权
    半导体存储器件包括垂直沟道晶体管

    公开(公告)号：US08830715B2

    公开(公告)日：2014-09-09

    申请号：US13304851

    申请日：2011-11-28

    申请人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    发明人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    IPC分类号： G11C5/02 ,  G11C11/34 ,  H01L27/108 ,  G11C7/02 ,  G11C7/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

    摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

    摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。

    Memory device having open bit line structure and method of sensing data therefrom
    4.
    发明授权
    Memory device having open bit line structure and method of sensing data therefrom 失效
    具有开放位线结构的存储器件和从其感测数据的方法

    公开(公告)号：US07580314B2

    公开(公告)日：2009-08-25

    申请号：US11649273

    申请日：2007-01-04

    申请人： Su-A Kim ,  Ki-Whan Song

    发明人： Su-A Kim ,  Ki-Whan Song

    IPC分类号： G11C8/00

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/10897

    摘要： A memory device includes a plurality of memory blocks. Each memory block includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells provided at intersections of the bit lines and word lines; a plurality of capacitors, and a plurality of sense amplifiers. Each sense amplifier has a first input and a second input. The first input is connected to a first bit line of a first one of the memory blocks and is coupled via one of the capacitors to a first bit line of a second one of the memory blocks. The second input of the input is connected to a second bit line of the second one of the memory blocks and is coupled via one of the capacitors to a second bit line of the first one of the memory blocks.

    摘要翻译： 存储器件包括多个存储器块。 每个存储块包括多个位线，多个字线，设置在位线和字线的交点处的多个存储单元; 多个电容器和多个读出放大器。 每个读出放大器具有第一输入和第二输入。 第一输入端连接到第一个存储器块的第一位线，并通过一个电容器耦合到第二个存储器块的第一位线。 输入的第二输入连接到第二存储器块的第二位线，并且经由电容器中的一个耦合到第一个存储器块的第二位线。

    MEMORY DEVICE CAPABLE OF QUICKLY REPAIRING FAIL CELL
    5.
    发明申请
    MEMORY DEVICE CAPABLE OF QUICKLY REPAIRING FAIL CELL 审中-公开
    能快速修复失败的记忆体

    公开(公告)号：US20160077940A1

    公开(公告)日：2016-03-17

    申请号：US14683705

    申请日：2015-04-10

    申请人： Jong-pil SON ,  Chul-woo PARK ,  Su-a KIM

    发明人： Jong-pil SON ,  Chul-woo PARK ,  Su-a KIM

    IPC分类号： G06F11/20

    CPC分类号： G06F11/2094 ,  G06F11/1048 ,  G06F2201/85 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/4402

    摘要： The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

    摘要翻译： 存储器件包括存储器阵列，控制逻辑和恢复电路。 存储器阵列具有被配置为存储数据的第一区域，被配置为存储故障小区信息的一部分的第二区域以及被配置为存储恢复信息的第三区域。 故障小区信息识别第一区域中的故障小区，并且恢复信息用于恢复存储在所识别的故障小区中的数据。 控制逻辑被配置为存储故障小区信息，将故障小区信息的一部分传送到存储器阵列的第二区域，并且基于访问请求中的地址信息确定是否执行恢复操作，并且部分 存储在第二区域中的故障小区信息。 访问请求是访问第一个区域的请求。 恢复电路被配置为执行恢复操作。

    MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    7.
    发明申请
    MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    存储核心和半导体存储器件，包括它们

    公开(公告)号：US20120212989A1

    公开(公告)日：2012-08-23

    申请号：US13304851

    申请日：2011-11-28

    申请人： Hak-Soo YU ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    发明人： Hak-Soo YU ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    IPC分类号： G11C5/02

    CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

    摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

    摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。

    RESISTIVE MEMORY
    8.
    发明申请
    RESISTIVE MEMORY 有权
    电阻记忆

    公开(公告)号：US20120020142A1

    公开(公告)日：2012-01-26

    申请号：US13184795

    申请日：2011-07-18

    申请人： Hak Soo Yu ,  In Gyu Baek ,  Hong Sun Hwang ,  Su A. Kim ,  Mu Jin Seo

    发明人： Hak Soo Yu ,  In Gyu Baek ,  Hong Sun Hwang ,  Su A. Kim ,  Mu Jin Seo

    IPC分类号： G11C11/00

    CPC分类号： G11C8/14 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71

    摘要： Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current.

    摘要翻译： 提供了半导体电阻式存储器件。 电阻式存储器件包括多个单元电池。 单位单元的源极线和数据输入/输出线可以被选择性地连接以具有基本上相同的电压电平以用于在单位电池处于非活动状态或未选择状态时进行均衡。 均衡可能会降低电流消耗并保护写入错误，并保护漏电流。

    Trap charge equalizing method and threshold voltage distribution reducing method
    9.
    发明授权
    Trap charge equalizing method and threshold voltage distribution reducing method 失效
    陷阱电荷均衡方法和阈值电压分布降低方法

    公开(公告)号：US08058187B2

    公开(公告)日：2011-11-15

    申请号：US12652052

    申请日：2010-01-05

    申请人： Ki-whan Song ,  Su-a Kim

    发明人： Ki-whan Song ,  Su-a Kim

    IPC分类号： H01L21/30

    CPC分类号： H01L27/11575 ,  G11C11/5671 ,  H01L27/10876 ,  H01L29/66833 ,  H01L29/792

    摘要： A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.

    摘要翻译： 一种方法降低半导体存储器件的晶体管中的阈值电压分布，其中每个晶体管包括氮化物衬垫。 该方法包括将电子注入到晶体管的氮化物衬垫内部和外部的电荷陷阱中，并且部分地去除注入氮化物衬垫内部和外部的电荷阱的电子，以平衡晶体管中的俘获电荷。

    TRAP CHARGE EQUALIZING METHOD AND THRESHOLD VOLTAGE DISTRIBUTION REDUCING METHOD
    10.
    发明申请
    TRAP CHARGE EQUALIZING METHOD AND THRESHOLD VOLTAGE DISTRIBUTION REDUCING METHOD 失效
    TRAP充电均衡方法和阈值电压分配减少方法

    公开(公告)号：US20100173503A1

    公开(公告)日：2010-07-08

    申请号：US12652052

    申请日：2010-01-05

    申请人： Ki-whan Song ,  Su-a Kim

    发明人： Ki-whan Song ,  Su-a Kim

    IPC分类号： H01L21/30

    CPC分类号： H01L27/11575 ,  G11C11/5671 ,  H01L27/10876 ,  H01L29/66833 ,  H01L29/792

    摘要： A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.

    摘要翻译： 一种方法降低半导体存储器件的晶体管中的阈值电压分布，其中每个晶体管包括氮化物衬垫。 该方法包括将电子注入到晶体管的氮化物衬垫内部和外部的电荷陷阱中，并且部分地去除注入氮化物衬垫内部和外部的电荷阱的电子，以平衡晶体管中的俘获电荷。