公开(公告)号：US07927932B2

公开(公告)日：2011-04-19

申请号：US12923471

申请日：2010-09-23

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC分类号： H01L21/84

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

摘要： A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

摘要翻译： 根据示例性实施例的半导体器件可以具有多个堆叠的晶体管。 半导体器件可以具有形成在半导体衬底上的下绝缘层和形成在下绝缘层上的上沟道体图案。 源极区域和漏极区域可以形成在上部通道主体图案内，并且非金属转移栅极电极可以设置在源极和漏极区域之间的上部通道主体图案上。 非金属转移栅电极，上通道体图案和下绝缘层可以被中间绝缘层覆盖。 金属字线可以设置在中间绝缘层内以接触非金属转移栅电极的至少上表面。 绝缘间隔物可以设置在金属字线的侧壁上。 金属节点插头可以设置在中间绝缘层和下绝缘层内以接触上通道主体图案的源区域。 示例性实施例还涉及制造上述半导体器件的方法。

公开(公告)号：US20110014754A1

公开(公告)日：2011-01-20

申请号：US12923471

申请日：2010-09-23

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC分类号： H01L21/8234

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

摘要： A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

公开(公告)号：US07825472B2

公开(公告)日：2010-11-02

申请号：US12219278

申请日：2008-07-18

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC分类号： H01L27/12

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

摘要： A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

摘要翻译： 根据示例性实施例的半导体器件可以具有多个堆叠的晶体管。 半导体器件可以具有形成在半导体衬底上的下绝缘层和形成在下绝缘层上的上沟道体图案。 源极区域和漏极区域可以形成在上部通道主体图案内，并且非金属转移栅极电极可以设置在源极和漏极区域之间的上部通道主体图案上。 非金属转移栅电极，上通道体图案和下绝缘层可以被中间绝缘层覆盖。 金属字线可以设置在中间绝缘层内以接触非金属转移栅电极的至少上表面。 绝缘间隔物可以设置在金属字线的侧壁上。 金属节点插头可以设置在中间绝缘层和下绝缘层内以接触上通道主体图案的源区域。 示例性实施例还涉及制造上述半导体器件的方法。

公开(公告)号：US20090020817A1

公开(公告)日：2009-01-22

申请号：US12219278

申请日：2008-07-18

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

摘要： A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

摘要翻译： 根据示例性实施例的半导体器件可以具有多个堆叠的晶体管。 半导体器件可以具有形成在半导体衬底上的下绝缘层和形成在下绝缘层上的上沟道体图案。 源极区域和漏极区域可以形成在上部通道主体图案内，并且非金属转移栅极电极可以设置在源极和漏极区域之间的上部通道主体图案上。 非金属转移栅电极，上通道体图案和下绝缘层可以被中间绝缘层覆盖。 金属字线可以设置在中间绝缘层内以接触非金属转移栅电极的至少上表面。 绝缘间隔物可以设置在金属字线的侧壁上。 金属节点插头可以设置在中间绝缘层和下绝缘层内以接触上通道主体图案的源区域。 示例性实施例还涉及制造上述半导体器件的方法。

公开(公告)号：US20090224330A1

公开(公告)日：2009-09-10

申请号：US12468415

申请日：2009-05-19

申请人： Chang Min Hong ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Kun-Ho Kwak ,  Byoung-Keun Son ,  Jong-Hoon Na ,  Yeon-Wook Jung ,  Ju-Young Lim

发明人： Chang Min Hong ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Kun-Ho Kwak ,  Byoung-Keun Son ,  Jong-Hoon Na ,  Yeon-Wook Jung ,  Ju-Young Lim

IPC分类号： H01L27/11 ,  H01L25/065 ,  H01L21/30

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor memory device and method of manufacturing the same are disclosed. The semiconductor memory device includes a semiconductor substrate having a cell region and a peripheral circuit region, first transistors provided on the semiconductor substrate, a first semiconductor layer provided on the first transistors, and bonded by a bonding technique, and second transistors provided on the first semiconductor layer, wherein the first and second transistors are provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer, respectively, and a metal layer is formed on gates of the first and second transistors respectively provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer. As a result, the transistors in the peripheral circuit region requiring high performance can be formed on an upper layer and a lower layer.

摘要翻译： 公开了一种半导体存储器件及其制造方法。 半导体存储器件包括具有单元区域和外围电路区域的半导体衬底，设置在半导体衬底上的第一晶体管，设置在第一晶体管上的第一半导体层，并通过接合技术接合，第二晶体管设置在第一晶体管上 半导体层，其中第一和第二晶体管分别设置在半导体衬底和第一半导体层的外围电路区域中，并且在分别设置在半导体衬底的外围电路区域中的第一和第二晶体管的栅极上形成金属层 半导体衬底和第一半导体层。 结果，可以在上层和下层上形成需要高性能的外围电路区域中的晶体管。

公开(公告)号：US08227919B2

公开(公告)日：2012-07-24

申请号：US12458391

申请日：2009-07-10

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L27/12

CPC分类号： H01L23/522 ,  H01L27/11 ,  H01L27/1108 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs.

摘要翻译： 提供一种互连结构和采用该互连结构的电子设备。 用于集成结构的互连结构包括设置在基板上的第一和第二接触插塞以及插入在第一和第二接触插塞的侧壁之间并且被配置为电连接第一和第二接触插塞的连接图案。

公开(公告)号：US07982221B2

公开(公告)日：2011-07-19

申请号：US12537521

申请日：2009-08-07

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L29/76

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US20100006942A1

公开(公告)日：2010-01-14

申请号：US12458391

申请日：2009-07-10

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L23/522 ,  H01L27/12

CPC分类号： H01L23/522 ,  H01L27/11 ,  H01L27/1108 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs.

摘要翻译： 提供一种互连结构和采用该互连结构的电子设备。 用于集成结构的互连结构包括设置在基板上的第一和第二接触插塞以及插入在第一和第二接触插塞的侧壁之间并且被配置为电连接第一和第二接触插塞的连接图案。

公开(公告)号：US07592625B2

公开(公告)日：2009-09-22

申请号：US11502397

申请日：2006-08-11

申请人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

发明人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L31/112

CPC分类号： G11C11/412 ,  G11C11/413 ,  Y10S257/903

摘要： Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 该器件可以包括包括外围区域和单元阵列区域的半导体衬底，其中，单元阵列区域中的衬底可以比周边区域低的凹槽，堆叠在单元阵列区域中的多个单元晶体管层，以及多个单元阵列区域 形成在外围区域的外围电路晶体管。 单元晶体管层可以形成在比周边区域更低的电池阵列区域中。

公开(公告)号：US20070047371A1

公开(公告)日：2007-03-01

申请号：US11502397

申请日：2006-08-11

申请人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

发明人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C11/413 ,  Y10S257/903

摘要： Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 该器件可以包括包括外围区域和单元阵列区域的半导体衬底，其中，单元阵列区域中的衬底可以比周边区域低的凹槽，堆叠在单元阵列区域中的多个单元晶体管层，以及多个单元阵列区域 形成在外围区域的外围电路晶体管。 单元晶体管层可以形成在比周边区域更低的电池阵列区域中。