公开(公告)号：US20070085165A1

公开(公告)日：2007-04-19

申请号：US11582388

申请日：2006-10-18

申请人： Han-Su Oh ,  Joo-Hyun Jeong

发明人： Han-Su Oh ,  Joo-Hyun Jeong

IPC分类号： H01L29/00

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor, a semiconductor device and methods of fabricating the same are disclosed. The capacitor may include a lower electrode, a dielectric layer covering an upper surface of the lower electrode and having a width wider than that of the lower electrode and an upper electrode covering an upper surface and sides of the dielectric layer. The semiconductor device may include a lower insulating layer on a lower line, the capacitor according to example embodiments, the lower electrode on the lower insulating layer and an upper insulating layer on the lower insulating layer and encompassing the capacitor.

摘要翻译： 公开了电容器，半导体器件及其制造方法。 电容器可以包括下电极，覆盖下电极的上表面的电介质层，其宽度大于下电极的宽度，上电极覆盖电介质层的上表面和侧面。 半导体器件可以包括在下一行上的下绝缘层，根据示例性实施例的电容器，下绝缘层上的下电极和下绝缘层上的上绝缘层并且包围电容器。

公开(公告)号：US06448611B1

公开(公告)日：2002-09-10

申请号：US09588546

申请日：2000-06-06

申请人： Han-Su Oh

发明人： Han-Su Oh

IPC分类号： H01L2976

CPC分类号： H01L29/402 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A high power semiconductor device and its fabrication method in which source and the drain regions are spaced apart from and edge of a field oxide layer. This allows the junction profile to become gently-sloped so that the junction breakdown voltage is increased. Also, since the edge of the field oxide layer is covered by the field plate and a ground voltage or below the ground voltage is applied to the field plate, the distribution of the strong electric field formed at the edge of the field oxide layer is dispersed, to further increase the junction breakdown voltage. Moreover, since the field plate covers the field oxide layer at the side of the drain of the high power semiconductor device, when a high voltage is applied to the drain, the electric field distribution is dispersed, so that the junction breakdown voltage at the edge of the gate electrode at the side of the drain can be increased.

摘要翻译： 一种高功率半导体器件及其制造方法，其中源极和漏极区域与场氧化物层间隔开和边缘。 这允许结型材变得轻轻地倾斜，使得结击穿电压增加。 此外，由于场氧化物层的边缘被场板覆盖，并且接地电压或接地电压以下施加到场板，所以形成在场氧化物层的边缘处的强电场的分布被分散 ，进一步增加结击穿电压。 此外，由于场板覆盖大功率半导体器件的漏极侧的场氧化物层，当向漏极施加高电压时，电场分布被分散，使得边缘处的结击穿电压 可以增加漏极侧的栅电极。

公开(公告)号：US07307335B2

公开(公告)日：2007-12-11

申请号：US11048715

申请日：2005-02-03

申请人： Dae-Hyun Kim ,  Han-Su Oh

发明人： Dae-Hyun Kim ,  Han-Su Oh

IPC分类号： H01L29/00 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/0808 ,  H01L27/0811 ,  H01L29/93 ,  H01L29/94

摘要： A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.

摘要翻译： 公开了具有MOS可变电抗器的半导体器件及其制造方法。 MOS变容二极管包括金属栅极电极，介于金属栅电极和半导体衬底之间的有源半导体板以及置于金属栅电极和有源半导体板之间的电容器介电层。 此外，下绝缘层使MOS变容二极管与半导体衬底绝缘。 根据本发明，使用金属栅电极来减少多余的耗尽，从而增加变容二极管的调谐范围，并且制造可靠的金属电阻器，而不需要额外的光掩模。

公开(公告)号：US20050179113A1

公开(公告)日：2005-08-18

申请号：US11048715

申请日：2005-02-03

申请人： Dae-Hyun Kim ,  Han-Su Oh

发明人： Dae-Hyun Kim ,  Han-Su Oh

IPC分类号： H01L27/04 ,  H01L27/08 ,  H01L27/108 ,  H01L29/93 ,  H01L29/94

CPC分类号： H01L27/0808 ,  H01L27/0811 ,  H01L29/93 ,  H01L29/94

摘要： A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.

摘要翻译： 公开了具有MOS可变电抗器的半导体器件及其制造方法。 MOS变容二极管包括金属栅极电极，介于金属栅电极和半导体衬底之间的有源半导体板以及置于金属栅电极和有源半导体板之间的电容器介电层。 此外，下绝缘层使MOS变容二极管与半导体衬底绝缘。 根据本发明，使用金属栅电极来减少多余的耗尽，从而增加变容二极管的调谐范围，并且制造可靠的金属电阻器，而不需要额外的光掩模。

公开(公告)号：US06613633B2

公开(公告)日：2003-09-02

申请号：US10207996

申请日：2002-07-31

申请人： Han-Su Oh

发明人： Han-Su Oh

IPC分类号： H01L21336

CPC分类号： H01L29/402 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A method to fabricate a high voltage transistor of a smart power device is discussed. The method includes forming a well of first conductivity in a substrate of second conductivity; forming a drift layer of the second conductivity in the well; forming a source region of the second conductivity in the well between a substrate/well junction and a well/drift layer junction; forming a drain region of the second conductivity in the drift layer, the drain region having relatively higher concentration of dopants relative to the drift layer; and forming a first field oxide layer on the drift layer such that the first field oxide layer is spaced apart from the drain region.

摘要翻译： 讨论了制造智能功率器件的高压晶体管的方法。 该方法包括在第二导电性基板中形成第一导电性的阱; 在井中形成第二导电性的漂移层; 在衬底/阱结与阱/漂移层结之间的阱中形成第二导电性的源极区; 在所述漂移层中形成所述第二导电性的漏极区，所述漏极区相对于所述漂移层具有相对较高的掺杂剂浓度; 以及在所述漂移层上形成第一场氧化物层，使得所述第一场氧化物层与所述漏极区间隔开。

公开(公告)号：US20150014788A1

公开(公告)日：2015-01-15

申请号：US14167236

申请日：2014-01-29

申请人： Min-Yeop Park ,  Leonelli Daniele ,  Shigenobu Maeda ,  Han-Su Oh ,  Woong-Gi Kim ,  Jong-Hyuk Lee ,  Ju-Seob Jeong

发明人： Min-Yeop Park ,  Leonelli Daniele ,  Shigenobu Maeda ,  Han-Su Oh ,  Woong-Gi Kim ,  Jong-Hyuk Lee ,  Ju-Seob Jeong

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a gate on a substrate, a gate insulating layer along a sidewall and a bottom surface of the gate, and an L-shaped spacer structure on both sidewalls of the gate. A structure extends the distance between the gate and source/drain regions to either side of the gate.

摘要翻译： 半导体器件包括衬底上的栅极，沿着侧壁的栅极绝缘层和栅极的底表面，以及在栅极的两个侧壁上的L形间隔结构。 结构将栅极和源极/漏极区域之间的距离延伸到栅极的任一侧。

公开(公告)号：US07611956B2

公开(公告)日：2009-11-03

申请号：US11941192

申请日：2007-11-16

申请人： Dae-Hyun Kim ,  Han-Su Oh

发明人： Dae-Hyun Kim ,  Han-Su Oh

IPC分类号： H01L21/20 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01L27/0808 ,  H01L27/0811 ,  H01L29/93 ,  H01L29/94

摘要： A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.

摘要翻译： 公开了具有MOS可变电抗器的半导体器件及其制造方法。 MOS变容二极管包括金属栅极电极，介于金属栅电极和半导体衬底之间的有源半导体板以及置于金属栅电极和有源半导体板之间的电容器介电层。 此外，下绝缘层使MOS变容二极管与半导体衬底绝缘。 根据本发明，使用金属栅电极来减少多余的耗尽，从而增加变容二极管的调谐范围，并且制造可靠的金属电阻器，而不需要额外的光掩模。