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    Efficient multi-symbol deinterleaver
    1.
    发明授权
    Efficient multi-symbol deinterleaver 有权
    高效的多符号解交织器

    公开(公告)号：US07954016B2

    公开(公告)日：2011-05-31

    申请号：US12717742

    申请日：2010-03-04

    申请人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    发明人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    IPC分类号： H03M13/03 ,  G06F11/00 ,  G11C29/00

    CPC分类号： H03M13/2764 ,  H03M13/2703

    摘要： Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

    摘要翻译： 本文公开的实施例解决了本领域对于有效的多符号解交织器的需要。 在一个方面，部署多个存储体以根据存储模式接收并同时存储多个值，诸如从调制星座确定的软判决值。 在另一方面，存储模式包括多个周期，多个存储体的选定子集和用于确定用于存储到为每个周期指示的相应存储体中的地址的地址偏移。 在另一方面，可以按顺序增加的索引（诸如地址）按顺序访问所存储的值。 还提出了各种其他方面。 这些方面具有允许以有效的方式解码多个符号值的好处，从而满足计算时间限制并节省功率。

    Efficient multi-symbol deinterleaver
    2.
    发明申请
    Efficient multi-symbol deinterleaver 有权
    高效的多符号解交织器

    公开(公告)号：US20050190864A1

    公开(公告)日：2005-09-01

    申请号：US10789605

    申请日：2004-02-27

    申请人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    发明人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    IPC分类号： H03M13/27 ,  H03M13/29 ,  H04L27/22 ,  H03D1/24

    CPC分类号： H03M13/2764 ,  H03M13/2703

    摘要： Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

    摘要翻译： 本文公开的实施例解决了本领域对于有效的多符号解交织器的需要。 在一个方面，部署多个存储体以根据存储模式接收并同时存储多个值，诸如从调制星座确定的软判决值。 在另一方面，存储模式包括多个周期，多个存储体的选定子集和用于确定用于存储到为每个周期指示的相应存储体中的地址的地址偏移。 在另一方面，可以按顺序增加的索引（诸如地址）按顺序访问所存储的值。 还提出了各种其他方面。 这些方面具有允许以有效的方式解码多个符号值的好处，从而满足计算时间限制并节省功率。

    EFFICIENT MULTI-SYMBOL DEINTERLEAVER
    3.
    发明申请
    EFFICIENT MULTI-SYMBOL DEINTERLEAVER 有权
    有效的多符号检测器

    公开(公告)号：US20100183096A1

    公开(公告)日：2010-07-22

    申请号：US12717742

    申请日：2010-03-04

    申请人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    发明人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    IPC分类号： H04L27/22 ,  G06F11/00 ,  H03M13/03

    CPC分类号： H03M13/2764 ,  H03M13/2703

    摘要： Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

    摘要翻译： 本文公开的实施例解决了本领域对于有效的多符号解交织器的需要。 在一个方面，部署多个存储体以根据存储模式接收并同时存储多个值，诸如从调制星座确定的软判决值。 在另一方面，存储模式包括多个周期，多个存储体的选定子集和用于确定用于存储到为每个周期指示的相应存储体中的地址的地址偏移。 在另一方面，可以按顺序增加的索引（诸如地址）按顺序访问所存储的值。 还提出了各种其他方面。 这些方面具有允许以有效的方式解码多个符号值的好处，从而满足计算时间限制并节省功率。

    Efficient multi-symbol deinterleaver
    4.
    发明授权
    Efficient multi-symbol deinterleaver 有权
    高效的多符号解交织器

    公开(公告)号：US07702968B2

    公开(公告)日：2010-04-20

    申请号：US10789605

    申请日：2004-02-27

    申请人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    发明人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    IPC分类号： H03M13/03 ,  G06F11/00 ,  G11C29/00

    CPC分类号： H03M13/2764 ,  H03M13/2703

    摘要： Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

    摘要翻译： 本文公开的实施例解决了本领域对于有效的多符号解交织器的需要。 在一个方面，部署多个存储体以根据存储模式接收并同时存储多个值，诸如从调制星座确定的软判决值。 在另一方面，存储模式包括多个周期，多个存储体的选定子集和用于确定用于存储到为每个周期指示的相应存储体中的地址的地址偏移。 在另一方面，可以按顺序增加的索引（诸如地址）按顺序访问所存储的值。 还提出了各种其他方面。 这些方面具有允许以有效的方式解码多个符号值的好处，从而满足计算时间限制并节省功率。

    Recursive realization of polynomial permutation interleaving
    6.
    发明授权
    Recursive realization of polynomial permutation interleaving 有权
    递归实现多项式置换交织

    公开(公告)号：US08397123B2

    公开(公告)日：2013-03-12

    申请号：US12571319

    申请日：2009-09-30

    申请人： Hanfang Pan ,  Michael A. Howard ,  Yongbin Wei ,  Michael A. Kongelf

    发明人： Hanfang Pan ,  Michael A. Howard ,  Yongbin Wei ,  Michael A. Kongelf

    IPC分类号： H03M13/00

    CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2764 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6525

    摘要： Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.

    摘要翻译： 描述了在turbo解码期间便于自动生成交错地址的系统和方法。 可以采用一种有效的递归技术，其中嵌套循环层能够从查询表中计算多项式和给定交织参数a和b的模块化函数。 使用递归技术，可以产生交织地址，每个时钟周期的一个交织地址可以保持turbo解码性能。

    Minimum finger low-power demodulator for wireless communication
    7.
    发明授权
    Minimum finger low-power demodulator for wireless communication 有权
    用于无线通信的最小手指低功耗解调器

    公开(公告)号：US08798214B2

    公开(公告)日：2014-08-05

    申请号：US11940313

    申请日：2007-11-14

    申请人： Michael Alexander Howard ,  June Namgoong ,  Hanfang Pan

    发明人： Michael Alexander Howard ,  June Namgoong ,  Hanfang Pan

    IPC分类号： H04B7/10

    CPC分类号： H04B1/7117

    摘要： Techniques for assigning multipaths to finger processors to achieve the desired data performance and low power consumption are described. A search is initially performed to obtain a set of multipaths for a transmission from at least one base station. At least one multipath (e.g., the minimum number of multipaths) having a combined performance metric (e.g., a combined SNR) exceeding a threshold is identified. The at least one multipath is assigned to, and processed by, at least one finger processor to recover the transmission from the base station(s).

    摘要翻译： 描述了将多路径分配给指状处理器以实现期望的数据性能和低功耗的技术。 最初执行搜索以获得用于来自至少一个基站的传输的一组多路径。 识别具有超过阈值的组合性能度量（例如，组合SNR）的至少一个多路径（例如，最小数量的多路径）。 至少一个多路径被分配给至少一个手指处理器并由其处理，以恢复来自基站的传输。

    Efficient zadoff-chu sequence generation
    8.
    发明授权
    Efficient zadoff-chu sequence generation 有权
    高效的zadoff-chu序列生成

    公开(公告)号：US08374072B2

    公开(公告)日：2013-02-12

    申请号：US12755998

    申请日：2010-04-07

    申请人： Peter Gaal ,  Robert J. Fuchs ,  Yongbin Wei ,  Ke Liu ,  Hanfang Pan ,  Durga Prasad Malladi ,  Daniel T. Macek

    发明人： Peter Gaal ,  Robert J. Fuchs ,  Yongbin Wei ,  Ke Liu ,  Hanfang Pan ,  Durga Prasad Malladi ,  Daniel T. Macek

    IPC分类号： H04J11/00 ,  H04W4/00

    CPC分类号： H04J13/0059 ,  H04J13/14

    摘要： Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters.

    摘要翻译： 用于Zadoff-Chu（Chu）序列生成的高效装置和方法避免了常规二次生成公式的附加处理和硬件复杂性，随后是具有产生Zadoff-Chu序列及其DFT的参考信号发生器的离散傅里叶变换（DFT）。 在无线通信系统（例如，长期演进（Long Term Evolution，LTE）系统）中，尤其在上行链路（UL）中广泛使用了Chu序列。 由于单载波操作模式，原则上发送Chu序列涉及一系列生成该序列，执行DFT操作，然后进行IFFT操作。 假设序列长度为N，则初始序列生成需要2N次乘法，并且DFT需要多于N个log 2（N）乘法。 鉴于Chu序列的频繁处理，这将代表一个复杂的负担。 除了可能计算某些初始参数之外，本发明使得可以执行没有任何乘法运算的序列生成和DFT步骤。

    SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING
    9.
    发明申请
    SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING 审中-公开
    用于信道解码的可调度调度器架构

    公开(公告)号：US20110280133A1

    公开(公告)日：2011-11-17

    申请号：US13104844

    申请日：2011-05-10

    申请人： Wei-Hsin Chang ,  Hanfang Pan ,  Michael Alexander Howard ,  Wenqing Wu

    发明人： Wei-Hsin Chang ,  Hanfang Pan ,  Michael Alexander Howard ,  Wenqing Wu

    IPC分类号： H04W72/04 ,  H04W24/00

    CPC分类号： H04L1/0052

    摘要： Certain aspects of the present disclosure relate to a method for processing wireless communications. According to one aspect, a processing unit may receive a plurality of code blocks of a transport block and schedule the plurality of code blocks to be decoded in parallel with a plurality of decoders. Each decoder decodes at least one code block as an independent tasks. The processing unit further collects the decoded information bits from the plurality of decoders and forwards the collected decoded information bits for further processing. In one aspect, the processing unit includes an output agent to temporarily store the decoded information bits while waiting for all code blocks of the transport block to be decoded.

    摘要翻译： 本公开的某些方面涉及一种用于处理无线通信的方法。 根据一个方面，处理单元可以接收传输块的多个码块，并且与多个解码器并行地调度要解码的多个码块。 至少一个解码器解码至少一个代码块作为独立任务。 处理单元进一步从多个解码器中收集解码的信息比特，并且转发所收集的解码信息比特用于进一步处理。 一方面，处理单元包括一个输出代理，用于临时存储解码的信息位，同时等待传输块的所有代码块被解码。