利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

50 条记录 (耗时 0.033 秒)

    Doping of semiconductor fin devices
    1.
    发明授权
    Doping of semiconductor fin devices 有权
    掺杂半导体鳍片器件

    公开(公告)号：US08790970B2

    公开(公告)日：2014-07-29

    申请号：US11446697

    申请日：2006-06-05

    申请人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66803

    摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

    摘要翻译： 半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。 每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。 掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。 相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

    Gate electrode for a semiconductor fin device
    2.
    发明申请
    Gate electrode for a semiconductor fin device 有权
    用于半导体鳍片器件的栅电极

    公开(公告)号：US20070111454A1

    公开(公告)日：2007-05-17

    申请号：US11649453

    申请日：2007-01-03

    申请人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

    摘要翻译： 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。 栅电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以引入和掺杂杂质的激活。 在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

    Doping of semiconductor fin devices
    3.
    发明申请
    Doping of semiconductor fin devices 有权

    公开(公告)号：US20060220133A1

    公开(公告)日：2006-10-05

    申请号：US11446890

    申请日：2006-06-05

    申请人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L27/12

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66803

    摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

    Doping of semiconductor fin devices
    5.
    发明授权
    Doping of semiconductor fin devices 有权
    掺杂半导体鳍片器件

    公开(公告)号：US07074656B2

    公开(公告)日：2006-07-11

    申请号：US10425156

    申请日：2003-04-29

    申请人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66803

    摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

    摘要翻译： 半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。 每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。 掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。 相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

    Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
    8.
    发明授权
    Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices 有权
    包含部分耗尽，完全耗尽和多栅极器件的绝缘体上半导体芯片

    公开(公告)号：US06720619B1

    公开(公告)日：2004-04-13

    申请号：US10319119

    申请日：2002-12-13

    申请人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L27148

    CPC分类号： H01L29/7854 ,  H01L29/66795

    摘要： The present disclosure provides a system and method for forming device on an insulator material. First, a semiconductor depletion material is formed with a predetermined height and width overlying a predetermined portion of the substrate to from an active region. An isolation material formed on top of the substrate surrounding the active region so as to bury a bottom portion of the active region therein, thereby exposing a top portion of the active region. A gate dielectric layer is deposited for covering the exposed the top and two sidewalls of the top portion of the active region, and at least one gate electrode is then formed on top of the gate dielectric layer and extending through two sidewalls thereof to reach the isolation material.

    摘要翻译： 本公开提供了一种用于在绝缘体材料上形成器件的系统和方法。 首先，半导体耗尽材料以预定的高度和宽度形成，该预定高度和宽度覆盖基板的预定部分至活性区域。 隔离材料形成在基板的顶部围绕有源区域，以便将有源区域的底部部分埋入其中，从而暴露有源区域的顶部部分。 沉积栅极电介质层以覆盖有源区顶部的顶部和两个侧壁的暴露，然后至少一个栅极电极形成在栅极电介质层的顶部并延伸通过其两个侧壁以达到隔离 材料。

    Silicon-on-insulator ULSI devices with multiple silicon film thicknesses
    9.
    发明授权
    Silicon-on-insulator ULSI devices with multiple silicon film thicknesses 有权
    具有多个硅膜厚度的绝缘体上硅ULSI器件

    公开(公告)号：US07141459B2

    公开(公告)日：2006-11-28

    申请号：US10388297

    申请日：2003-03-12

    申请人： Fu-Liang Yang ,  Hao-Yu Chen ,  Yee-Chia Yeo ,  Carlos H. Diaz ,  Chenming Hu

    发明人： Fu-Liang Yang ,  Hao-Yu Chen ,  Yee-Chia Yeo ,  Carlos H. Diaz ,  Chenming Hu

    IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/36 ,  H01L21/8238

    CPC分类号： H01L21/7624 ,  H01L21/84 ,  H01L27/1203

    摘要： A method of forming a multiple-thickness semiconductor-on-insulator, comprising the following steps. A wafer is provided comprising a semiconductor film (having at least two regions) overlying a buried insulator layer overlying a substrate. The semiconductor film within one of the at least two regions is masked to provide at least one semiconductor film masked portion having a first thickness, leaving exposed the semiconductor film within at least one of the at least two regions to provide at least one semiconductor film exposed portion having the first thickness. In one embodiment, at least a portion of the at least one exposed semiconductor film portion is oxidized to provide at least one partially oxidized, exposed semiconductor film portion. Then the oxidized portion of the exposed semiconductor film is removed to leave a portion of the semiconductor film having a second thickness less than the first thickness.

    摘要翻译： 一种形成多层绝缘体半导体的方法，包括以下步骤。 提供晶片，其包括覆盖在衬底上的掩埋绝缘体层的半导体膜（具有至少两个区域）。 至少两个区域之一内的半导体膜被掩模以提供具有第一厚度的至少一个半导体膜掩模部分，使半导体膜暴露在至少两个区域中的至少一个区域中，以提供至少一个半导体膜暴露 具有第一厚度的部分。 在一个实施例中，所述至少一个暴露的半导体膜部分的至少一部分被氧化以提供至少一个部分氧化的暴露的半导体膜部分。 然后去除暴露的半导体膜的氧化部分，以留下具有小于第一厚度的第二厚度的半导体膜的一部分。

    Gate electrode for a semiconductor fin device
    10.
    发明申请
    Gate electrode for a semiconductor fin device 有权
    用于半导体鳍片器件的栅电极

    公开(公告)号：US20050233525A1

    公开(公告)日：2005-10-20

    申请号：US10825872

    申请日：2004-04-16

    申请人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

    摘要翻译： 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。 栅极电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以跟随掺杂剂杂质的引入和激活。 在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。