公开(公告)号：US06833569B2

公开(公告)日：2004-12-21

申请号：US10328234

申请日：2002-12-23

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin C. Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin C. Jones

IPC分类号： H01L27148

CPC分类号： H01L29/66916 ,  H01L29/42316 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/802

摘要： The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.

摘要翻译： 本发明提供一种用于制造具有与前门对准的背栅的平面DGFET的方法。 本发明的方法通过在后门的一部分中产生载流子耗尽区来实现该对准。 载流子耗尽区减小了源极/漏极区域和后栅极之间的电容，从而提供了高性能自对准平面双栅极场效应晶体管（DGFET）。 本发明还提供一种具有与前门对准的后门的平面DGFET。 通过在后门的部分中提供载流子耗尽区来实现前到后栅极对准。

公开(公告)号：US06762443B2

公开(公告)日：2004-07-13

申请号：US10298834

申请日：2002-11-18

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H01L27148

CPC分类号： H01L29/78612 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/78642

摘要： In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolation trench. A vertical transistor that is used, for example, in a DRAM memory cell and a method for making the transistor includes connecting the channel region of the vertical transistor to the substrate by disposing a conductive layer in the isolation trench between a lower insulation filling and an upper insulation filling.

摘要翻译： 在DRAM存储单元中，各个存储单元通过隔离沟槽（STI）彼此隔离。 在这种情况下，作为SOI晶体管由隔离沟槽形成垂直晶体管，因为其沟道区域通过隔离沟槽与衬底隔离。 例如在DRAM存储单元中使用的垂直晶体管和制造晶体管的方法包括通过在隔离沟槽中设置导电层来将垂直晶体管的沟道区域连接到衬底，该导电层位于下部绝缘填充物和 上部绝缘填充。

公开(公告)号：US06717190B2

公开(公告)日：2004-04-06

申请号：US10366672

申请日：2003-02-14

申请人： Makoto Shizukuishi

发明人： Makoto Shizukuishi

IPC分类号： H01L27148

CPC分类号： H01L27/14812 ,  H01L27/14831 ,  H01L27/14843 ,  H01L29/42396

摘要： A honeycomb CCD, whose light receiving portion and a certain light receiving portion 105 adjoining thereto are arranged at a position to be shifted by half a pixel pitch in line and row directions, has charge transfer electrodes 111-114 formed of double-layered polysilicon electrode, a metal wiring 125, having smaller resistivity thereto, which is arranged in the longitudinal direction along each VCCD to intersect and cross over the charge transfer electrodes 111-114 being connected by a contact hole 126, by which electrical resistance of the polysilicon layer of the charge transfer electrodes can be lowered without increasing thickness thereof.

摘要翻译： 将其光接收部分和与其相邻的特定光接收部分105布置在行和行方向上偏移半个像素间距的蜂窝CCD具有由双层多晶硅电极形成的电荷转移电极111-114 具有较小的电阻率的金属布线125沿着每个VCCD在纵向方向上布置以交叉并交叉通过接触孔126连接的电荷转移电极111-114，由此，多晶硅层的电阻 可以在不增加电荷转移电极的厚度的情况下降低电荷转移电极。

公开(公告)号：US06603171B2

公开(公告)日：2003-08-05

申请号：US10225315

申请日：2002-08-20

申请人： Alessandro Grossi ,  Cesare Clementi

发明人： Alessandro Grossi ,  Cesare Clementi

IPC分类号： H01L27148

CPC分类号： H01L27/11526 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11536

摘要： A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

摘要翻译： 一种用于制造包括存储单元的电子器件的方法，包括在半导体材料的衬底上形成包括浮动栅极区域，中间电介质区域和控制栅极区域的多层堆叠; 形成在衬底的顶部和多层叠层之间延伸并具有至少等于多层叠层的高度的保护层。 形成多层堆叠的步骤包括在所有侧面上限定控制栅极区域的步骤，使得每个控制栅极区域与相邻的控制栅极区域完全分离。 保护层将多层堆叠在两侧彼此隔离。 金属字线在保护层上方延伸并与栅极区域电接触。

公开(公告)号：US06590238B1

公开(公告)日：2003-07-08

申请号：US10074519

申请日：2002-02-12

申请人： Christopher Parks

发明人： Christopher Parks

IPC分类号： H01L27148

CPC分类号： H01L27/148 ,  H01L29/76816

摘要： A charge-coupled device includes a plurality of cells for forming the charge-coupled device, each of the cells capable of retaining charge a transfer mechanism within the charge-coupled device for moving charge through the plurality of cells, an output region for receiving charge moved through the plurality of cells under control of the transfer mechanism; a floating diffusion to receive charge moved across the output region; a reset gate to remove charge from the floating diffusion and reset the floating diffusion to a reference voltage level; and a capacitance control gate adjacent to the floating diffusion for canceling capacitance coupling of the reset gate. A capacitance control gate covers a portion of the floating diffusion. The capacitance control gate voltage is adjusted to alter the capacitance of the floating diffusion. The capacitance control gate is clocked opposite that of the reset gate to cancel the capacitive effects of the reset gate.

摘要翻译： 电荷耦合器件包括用于形成电荷耦合器件的多个单元，每个单元能够在电荷耦合器件内保持一个传输机制，用于通过多个单元移动电荷;输出区域，用于接收电荷 在传送机构的控制下移动通过多个单元; 用于接收电荷的浮动扩散在整个输出区域上移动; 复位门，以从浮动扩散中去除电荷并将浮动扩散重置为参考电压电平; 以及与浮动扩散相邻的电容控制栅极，用于消除复位栅极的电容耦合。 电容控制栅极覆盖浮动扩散部分。 调整电容控制栅极电压以改变浮动扩散的电容。 电容控制栅极与复位栅极的时钟相反，以消除复位栅极的电容效应。

公开(公告)号：US06586784B1

公开(公告)日：2003-07-01

申请号：US10263169

申请日：2002-10-02

申请人： Christopher Parks

发明人： Christopher Parks

IPC分类号： H01L27148

CPC分类号： H04N5/37213 ,  H01L27/14825 ,  H01L29/7685 ,  H01L29/76858 ,  H04N5/361

摘要： A method for reducing dark current within a charge coupled device includes the steps of providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second conductivity type, and a clock driver for causing the transfer of charge through the charge coupled device; providing a barrier for separating charge packets when in accumulation state; applying, at a first time period, voltages to all phases of gates sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers; after the first time period, applying, at each gate phase n having a capacitance Cn to the layer of the second conductivity type, a voltage change on the gate phase n given by &Dgr;Vn such that the sum of products of the capacitances and voltage changes is substantially zero ∑ n ⁢   ⁢ C n ⁢ Δ ⁢   ⁢ V n ≅ 0 ; after the voltage changes required to transfer charge through the charge coupled device, returning the voltages of all phases of gates back to the voltage sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers.

摘要翻译： 一种用于减小电荷耦合器件内的暗电流的方法包括以下步骤：在第二导电类型的阱或衬底中提供由绝缘层与第一导电类型的掩埋沟道隔开的三相或更多相的相位，以及时钟 驱动器，用于通过电荷耦合器件传输电荷; 提供在积聚状态下分离电荷包的屏障; 在第一时间段施加足以使第一导电类型的表面由暗电流还原电荷载流子累积的门的所有相的电压; 在第一时间段之后，在具有第二导电类型的层的电容Cn的每个栅相n处施加由DELTAVn给出的栅相n的电压变化，使得电容和电压变化的乘积之和为 在将电荷转移通过电荷耦合器件所需的电压变化之后基本上为零，将栅极的所有相的电压返回到足以使第一导电类型的表面由暗电流减小的电荷载流子积累的电压。

公开(公告)号：US06580106B2

公开(公告)日：2003-06-17

申请号：US10043419

申请日：2002-01-10

申请人： Jaroslav Hynecek

发明人： Jaroslav Hynecek

IPC分类号： H01L27148

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/14656 ,  H01L31/1105

摘要： In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.

公开(公告)号：US06555855B2

公开(公告)日：2003-04-29

申请号：US09750065

申请日：2000-12-29

申请人： Yukiya Kawakami

发明人： Yukiya Kawakami

IPC分类号： H01L27148

CPC分类号： H01L27/14818 ,  H01L27/14806

摘要： Minority carriers generated by photoelectric conversion in an isolation layer and a semiconductor region with the same conduction type as that of the isolation layer are provided with an effective diffusion length owing to a trench formed in the isolation layer and with no path, which could be a straight escape route for the minority carriers, and false signals, therefore, scarcely enters to a neighboring cell, so that smear and color interference can be suppressed.

摘要翻译： 通过隔离层中的光电转换和与隔离层相同的导电类型的半导体区域产生的少数载流子由于在隔离层中形成的沟槽而没有路径而被提供有效的扩散长度，其可以是 因此，少数载体的直线逃逸路线和伪信号几乎不会进入邻近的小区，从而可以抑制污迹和颜色干扰。

公开(公告)号：US06476426B1

公开(公告)日：2002-11-05

申请号：US09347552

申请日：1999-07-06

申请人： Jennifer J. Patterson ,  Mark S. Swenson ,  Clifford I. Drowley

发明人： Jennifer J. Patterson ,  Mark S. Swenson ,  Clifford I. Drowley

IPC分类号： H01L27148

CPC分类号： H01L27/14825 ,  H01L27/14812

摘要： An electronic component having an image sensing device (41, 71, 86, 132, 182, 212) and a method for improving pixel charge transfer in the image sensing device (41, 71, 86, 132, 182, 212). The image sensing device (41, 71, 86, 132, 182, 212) has a transfer gate (42, 82) between a source region (43, 83) and an image sensing region. The image sensing region is formed to have a wider device width proximate to the transfer gate (42, 82) than at a point distal from the transfer gate (42, 82).

摘要翻译： 一种具有图像感测装置（41,71,86,132,182,212）的电子部件和用于改善图像感测装置（41,71,86,132,182,212）中的像素电荷转移的方法。 图像感测装置（41,71,86,132,182,212）在源区域（43,83）和图像感测区域之间具有传输门（42,82）。 图像感测区域形成为具有靠近传送门（42,82）的较宽的器件宽度，远离传输门（42,82）。

公开(公告)号：US06472698B1

公开(公告)日：2002-10-29

申请号：US09665903

申请日：2000-09-20

申请人： Yasutaka Nakashiba

发明人： Yasutaka Nakashiba

IPC分类号： H01L27148

CPC分类号： H01L27/14685 ,  H01L27/14601 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636

摘要： In a solid state image sensor having micro lenses, the micro lens and a bonding pad electrode are formed on a planarizing layer. Thus, it is no longer necessary to etch the planarizing layer for exposing the bonding pad under the planarizing layer, by use of a photolithography, and therefore, it is possible to avoid dissolution, deform and detachment of the micro lens, which would have otherwise been caused in the prior art by dissolving a photoresist which was used in the photolithography.

摘要翻译： 在具有微透镜的固态图像传感器中，在平坦化层上形成微透镜和焊盘电极。 因此，通过使用光刻法，不需要蚀刻用于使平坦化层下的接合焊盘露出的平坦化层，因此可以避免微透镜的溶解，变形和分离，否则将会另外 在现有技术中通过溶解光刻胶中使用的光致抗蚀剂引起。