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75 条记录 (耗时 0.056 秒)

    Multifunction input/output circuit
    7.
    发明授权
    Multifunction input/output circuit 有权
    多功能输入/输出电路

    公开(公告)号：US08217700B1

    公开(公告)日：2012-07-10

    申请号：US12496590

    申请日：2009-07-01

    申请人： Timothy Williams ,  Harold Kutz ,  Warren Snyder ,  David G. Wright

    发明人： Timothy Williams ,  Harold Kutz ,  Warren Snyder ,  David G. Wright

    IPC分类号： H03L5/00

    CPC分类号： H03K19/1732

    摘要： In one example, a chip includes integrated components configured to operate in the digital domain and the analog domain. An I/O pad located on the chip is configured to provide an external device access to the integrated components. A multifunction I/O interface cell between the I/O pad and the integrated components is configured to selectively connect different combinations of the components to the same I/O pad at different times. The multifunction I/O interface cell may include a first switching device connected to ground, a second switching device connected to a reference voltage, an analog input/output buffer, and a digital input/output buffer.

    摘要翻译： 在一个示例中，芯片包括被配置为在数字域和模拟域中操作的集成组件。 位于芯片上的I / O焊盘被配置为提供对集成部件的外部设备访问。 I / O焊盘和集成组件之间的多功能I / O接口单元被配置为在不同时间有选择地将组件的不同组合连接到相同的I / O焊盘。 多功能I / O接口单元可以包括连接到地的第一开关器件，连接到参考电压的第二开关器件，模拟输入/输出缓冲器和数字输入/输出缓冲器。

    Method and circuit for providing a system level reset function for an electronic device
    8.
    发明授权
    Method and circuit for providing a system level reset function for an electronic device 有权
    为电子设备提供系统电平复位功能的方法和电路

    公开(公告)号：US07089133B1

    公开(公告)日：2006-08-08

    申请号：US10942523

    申请日：2004-09-15

    申请人： Timothy Williams ,  Harold Kutz ,  Eric Blom ,  Warren Snyder

    发明人： Timothy Williams ,  Harold Kutz ,  Eric Blom ,  Warren Snyder

    IPC分类号： G06F19/00 ,  G06F1/24

    CPC分类号： G06F1/24

    摘要： A method and circuit provide a system level reset function for an electronic device. An initial reset function is provided under a low voltage condition of supply voltage, such as occur upon first energizing the electronic device. A tunable reset function is also provided, which can first be asserted at a voltage level setting less precise than that setting becomes upon tuning. Further, a boot-up reset function is provided, which provides its reset function at a voltage level setting that is set according to a calibration. Calibration can be based on data stored in a non-volatile memory, and can involve a checksum operation. The electronic device, a microcontroller for instance, is held in a reset state with any of the initial, tunable, and boot-up reset functions.

    摘要翻译： 方法和电路为电子设备提供系统级复位功能。 在电源电压的低电压条件下提供初始复位功能，例如在电子设备首次通电时发生。 还提供了可调谐复位功能，其可以首先在比调谐时设置的精度低的电压电平设置下被断言。 此外，提供启动复位功能，其提供其按照校准设置的电压电平设置的复位功能。 校准可以基于存储在非易失性存储器中的数据，并且可以涉及校验和操作。 例如，电子设备（例如微控制器）被保持在具有任何初始，可调谐和启动复位功能的复位状态。

    Emulator chip/board architecture and interface
    9.
    发明授权
    Emulator chip/board architecture and interface 失效
    仿真器芯片/板结构和接口

    公开(公告)号：US07076420B1

    公开(公告)日：2006-07-11

    申请号：US09975030

    申请日：2001-10-10

    申请人： Warren Snyder ,  Craig Nemecek ,  Bert Sullam

    发明人： Warren Snyder ,  Craig Nemecek ,  Bert Sullam

    IPC分类号： G06F9/455

    CPC分类号： G06F11/3656

    摘要： A communication interface for an in-circuit emulation system. The interface uses four pins between a virtual microcontroller (an FPGA emulating a microcontroller) and a real microcontroller under test. The bus is fast enough to allow the two devices to operate in synchronization. I/O reads, interrupt vector information and watchdog information is provided over the bus in a time fast enough to allow execution in lock step. Two data lines are provided, one is bi-directional and one is driven only by the microcontroller. A system clock is provided and the microcontroller supplies its clock signal to the FPGA since the microcontroller can operate at varying clock speeds. The bus is time-dependent so more information can be placed on this reduced-pin count bus. Therefore, instructions and data are distinguished based on the time the information is sent within the sequence. The bus can be used to carry trace information, program the flash memory on the microcontroller, perform test control functions, etc.

    摘要翻译： 用于在线仿真系统的通信接口。 该接口在虚拟微控制器（仿真微控制器的FPGA）和正在测试的真实微控制器之间使用四个引脚。 总线足够快以允许两个设备同步运行。 I / O读取，中断向量信息和看门狗信息通过总线提供足够快的时间，以允许在锁定步骤中执行。 提供两条数据线，一条是双向的，一条仅由微控制器驱动。 提供系统时钟，微控制器将其时钟信号提供给FPGA，因为微控制器可以以不同的时钟速度工作。 总线是时间依赖的，所以更多的信息可以放在这个减少针数的总线上。 因此，指令和数据是根据序列中发送信息的时间来区分的。 总线可用于携带跟踪信息，在微控制器上编程闪存，执行测试控制功能等。

    System level interconnect with programmable switching
    10.
    发明授权
    System level interconnect with programmable switching 有权
    系统级互连与可编程切换

    公开(公告)号：US08026739B2

    公开(公告)日：2011-09-27

    申请号：US11965677

    申请日：2007-12-27

    申请人： Bert Sullam ,  Warren Snyder ,  Haneef Mohammed

    发明人： Bert Sullam ,  Warren Snyder ,  Haneef Mohammed

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/173 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/1776

    摘要： Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

    摘要翻译： 不同的功能元件都位于相同的集成电路中，其中至少一个功能元件包括微控制器。 集成电路中的配置寄存器或配置存储器存储由微控制器加载的配置值。 连接器配置为将集成电路连接到外部信号。 位于集成电路中的系统级互连可根据加载到配置寄存器中的配置值可编程地将不同功能元件和不同连接器连接在一起。