公开(公告)号：US20100025739A1

公开(公告)日：2010-02-04

申请号：US12533740

申请日：2009-07-31

申请人： Haruka SHIMIZU ,  Natsuki YOKOYAMA

发明人： Haruka SHIMIZU ,  Natsuki YOKOYAMA

IPC分类号： H01L29/808 ,  H01L21/337

CPC分类号： H01L29/0619 ,  H01L29/0661 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/8083

摘要： A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.

摘要翻译： 提供了其中通道电阻降低而不降低其阻断电压的常闭型结型FET。 在使用由碳化硅制成的衬底形成的结型FET中，使沟道区（第二外延层）的杂质浓度高于作为漂移层的第一外延层的杂质浓度。 沟道区域由沟道宽度恒定的第一区域和沟道宽度朝向漏极（衬底）侧变宽的第一区域下方的第二区域形成。 第一外延层和第二外延层之间的边界位于沟道宽度朝向漏极（基板）侧变宽的第二区域中。

公开(公告)号：US20110018004A1

公开(公告)日：2011-01-27

申请号：US12834764

申请日：2010-07-12

申请人： Haruka SHIMIZU ,  Natsuki Yokoyama

发明人： Haruka SHIMIZU ,  Natsuki Yokoyama

IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L21/336 ,  H01L29/201

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66734

摘要： There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.

摘要翻译： 制造含有具有大的沟道迁移率的UMOSFET的半导体功率器件并且其阈值电压可以降低而没有阻断电压的损失是没有有效的方法。 利用具有p体浓度低的狭窄区域和p体浓度高的宽区域的碳化硅沟槽MOSFET来提供具有大阻断电压的半导体器件。

公开(公告)号：US20130056754A1

公开(公告)日：2013-03-07

申请号：US13655040

申请日：2012-10-18

申请人： Haruka SHIMIZU ,  Natsuki YOKOYAMA

发明人： Haruka SHIMIZU ,  Natsuki YOKOYAMA

IPC分类号： H01L29/161 ,  H01L27/088

CPC分类号： H01L27/0629 ,  H01L21/8213 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1608 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/868 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

摘要： A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.

公开(公告)号：US20110220916A1

公开(公告)日：2011-09-15

申请号：US13042528

申请日：2011-03-08

申请人： Haruka SHIMIZU ,  Natsuki YOKOYAMA

发明人： Haruka SHIMIZU ,  Natsuki YOKOYAMA

IPC分类号： H01L29/24

CPC分类号： H01L27/0629 ,  H01L21/8213 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1608 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/868 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

摘要： A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.

摘要翻译： 常闭型碳化硅结FET由于其特性的劣化而具有栅极不易使用的问题。 出现此问题的原因是为了实现常关，栅极电压应在0V关断，同时将导通状态栅极电压抑制在约2.5V，以防止电流通过pn 门和源之间的连接。 因此，从阈值电压到导通状态栅极电压的范围仅为约1V至2V，并且难以控制栅极电压。 在本发明中提供的是通过将常闭型碳化硅结FET的栅极耦合到具有等于或稍小于结FET的栅极电容的电容的元件而获得的电子电路器件。

公开(公告)号：US20110198613A1

公开(公告)日：2011-08-18

申请号：US13020125

申请日：2011-02-03

申请人： Haruka SHIMIZU ,  Natsuki YOKOYAMA

发明人： Haruka SHIMIZU ,  Natsuki YOKOYAMA

IPC分类号： H01L29/24 ,  H01L29/20 ,  H01L21/336

CPC分类号： H01L29/1608 ,  H01L29/0603 ,  H01L29/0696 ,  H01L29/1066 ,  H01L29/66068 ,  H01L29/8083

摘要： The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n+ type layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a p+ type gate region and an n+ type source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.

摘要翻译： 在使用碳化硅衬底的接合FET中，在栅极和源极之间的pn结区域中产生的漏电流减小。 在使用碳化硅衬底的沟槽结FET中，将氮引入到沟槽的侧壁和底表面中，从而在沟槽的表面上形成n型层和n +型层。 以这种方式，对应于p +型栅极区域和n +型源极区域之间的结区域的pn结区域在半导体衬底的主表面上而不是在沟槽的受损侧壁上暴露，并且暴露区域 其变窄。 因此，可以降低pn结区域中的漏电流。