公开(公告)号：US06751153B2

公开(公告)日：2004-06-15

申请号：US10187048

申请日：2002-06-28

申请人： Yasumichi Mori ,  Ken Sumitani ,  Yuji Tanaka ,  Haruyasu Fukui

发明人： Yasumichi Mori ,  Ken Sumitani ,  Yuji Tanaka ,  Haruyasu Fukui

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A non-volatile semiconductor memory device, comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a first address inversion section for inverting or non-inverting the logical values of at least a specific bit of the input address signal and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal.

摘要翻译： 一种非易失性半导体存储器件，包括多个存储单元，每个存储单元包括多个存储器单元，用于识别外部输入的命令信号并输出​​识别信号的命令识别单元，用于产生用于执行的控制信号的内部控制单元 由识别信号指定的命令，地址控制部分，用于根据外部输入的地址信号，向包括要访问的多个存储体组的任意组合的存储区域产生内部地址信号;以及第一地址转换部分 用于反相或非反相输入地址信号的至少一个特定位的逻辑值，并将结果输入地址信号输出到地址控制部分。 基于控制信号和内部地址信号来访问预定的存储单元。

公开(公告)号：US06646947B2

公开(公告)日：2003-11-11

申请号：US10184133

申请日：2002-06-26

申请人： Haruyasu Fukui ,  Ken Sumitani ,  Yasumichi Mori

发明人： Haruyasu Fukui ,  Ken Sumitani ,  Yasumichi Mori

IPC分类号： G11C700

CPC分类号： G06F13/28

摘要： A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.

摘要翻译： 本发明的数据传输控制装置包括：用于识别输入控制命令的命令识别部分; 第一地址输出部分，用于基于输入的控制命令来控制数据传送地址的输出和存储顺序以及数据传送完成地址; 第一存储器地址存储部分，用于存储从第一地址输出部分输出的第一存储器阵列的数据传输开始地址; 第二存储器地址存储部分，用于存储从第一地址输出部分输出的第二存储器阵列的数据传输开始地址; 第三存储器地址存储部分，用于存储从第一地址输出部分输出的数据传输完成地址。

公开(公告)号：US06549475B2

公开(公告)日：2003-04-15

申请号：US10183857

申请日：2002-06-25

申请人： Ken Nakazawa ,  Ken Sumitani ,  Haruyasu Fukui ,  Yasumichi Mori

发明人： Ken Nakazawa ,  Ken Sumitani ,  Haruyasu Fukui ,  Yasumichi Mori

IPC分类号： G11C1604

CPC分类号： G11C7/22

摘要： A semiconductor memory device in which an input command controls an operation includes a command state machine for decoding the input command and outputting the decoding result; a plurality of status registers for storing state information of the semiconductor memory device; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of data to a second data bus. At least the first switching circuit, among the first and second switching circuits, is controlled by the decoding result output by the command state machine.

公开(公告)号：US06785185B2

公开(公告)日：2004-08-31

申请号：US10183742

申请日：2002-06-25

申请人： Ken Sumitani ,  Haruyasu Fukui

发明人： Ken Sumitani ,  Haruyasu Fukui

IPC分类号： G11C800

CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2245

摘要： A semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command while allowing a memory operation to at least one of the first and second memory sections. At least one of the first and second memory sections include a plurality of small memory regions, and the memory control section allows each of the plurality of small memory regions to be separately and simultaneously subjected to an access operation.

摘要翻译： 半导体存储器件包括包括多个存储器元件的第一和第二存储器部分，以及存储器控制部分，用于基于外部控制命令允许第一和第二存储器部分之间的数据传送操作，同时允许存储器操作至少一个 的第一和第二存储器部分。 第一和第二存储器区域中的至少一个包括多个小存储器区域，并且存储器控制部件允许多个小存储器区域中的每一个被单独地并且同时进行访问操作。

公开(公告)号：US06522581B2

公开(公告)日：2003-02-18

申请号：US09881315

申请日：2001-06-12

申请人： Hidekazu Takata ,  Haruyasu Fukui ,  Ken Sumitani

发明人： Hidekazu Takata ,  Haruyasu Fukui ,  Ken Sumitani

IPC分类号： G11C1604

CPC分类号： G11C11/005

摘要： A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device, a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.

摘要翻译： 半导体存储装置包括：多个第一存储器阵列，每个第一存储器阵列包括多个半导体存储元件，其中写入来自外部设备的数据，并且从该数据读出数据到外部设备;第二存储器阵列，其操作 与多个第一存储器阵列分开并且包括包括多个非易失性半导体存储元件的至少一个块; 以及数据传送部分，用于在多个第一存储器阵列和第二存储器阵列之间传送数据。

公开(公告)号：US06292392B1

公开(公告)日：2001-09-18

申请号：US09163714

申请日：1998-09-30

申请人： Haruyasu Fukui

发明人： Haruyasu Fukui

IPC分类号： G11C1604

CPC分类号： G11C16/3445 ,  G11C16/26 ,  G11C16/28 ,  G11C16/344 ,  G11C2216/22

摘要： A non-volatile memory device includes: a plurality of memory cell arrays including a plurality of blocks, each block including a matrix of memory cells coupled to one another via word lines and bit lines such that corresponding ones of the word line in the plurality of blocks of each memory cell array are coupled to a common, the word lines being commonly driven by decoders respectively provided for the memory cell arrays, where all data stored in each block is subject to erasure in one erase operation, the non-volatile memory device further including: a plurality of sense amplifiers for reading data from the memory cells; and a control circuit for simultaneously performing a plurality of operations by using the plurality of sense amplifiers.

摘要翻译： 非易失性存储器件包括：包括多个块的多个存储单元阵列，每个块包括经由字线和位线彼此耦合的存储器单元的矩阵，使得多个块中的字线相应的 每个存储单元阵列的块被耦合到共同的，字线通常由分别为存储单元阵列提供的解码器驱动，其中存储在每个块中的所有数据在一次擦除操作中被擦除，非易失性存储器件 还包括：用于从所述存储器单元读取数据的多个读出放大器; 以及用于通过使用多个读出放大器同时执行多个操作的控制电路。

公开(公告)号：US06157242A

公开(公告)日：2000-12-05

申请号：US272248

申请日：1999-03-19

申请人： Haruyasu Fukui

发明人： Haruyasu Fukui

IPC分类号： G11C16/06 ,  H02M3/07 ,  G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M2003/075 ,  H02M2003/076

摘要： In a charge pump for providing a desired boosted output voltage, a plurality of boosting stages are connected in series. The pump also has a clock signal supply circuit for providing clock signals and a boost circuit for boosting the clock signals. Clock signals derived from the clock signal supply circuit are supplied to each of the boosting stages on a former side. In contrast, a boosted clock signal derived from the clock signal boost circuit and a clock signal derived from the clock signal supply circuit are supplied to each of the boosting stages on a latter side.

摘要翻译： 在用于提供期望的升压输出电压的电荷泵中，多个升压级串联连接。 泵还具有用于提供时钟信号的时钟信号供应电路和用于升压时钟信号的升压电路。 从时钟信号供给电路得到的时钟信号被提供给前一侧的每个升压级。 相反，从时钟信号升压电路得到的升压时钟信号和从时钟信号供给电路导出的时钟信号被提供给后一侧的每个升压级。