公开(公告)号：US06751153B2

公开(公告)日：2004-06-15

申请号：US10187048

申请日：2002-06-28

申请人： Yasumichi Mori ,  Ken Sumitani ,  Yuji Tanaka ,  Haruyasu Fukui

发明人： Yasumichi Mori ,  Ken Sumitani ,  Yuji Tanaka ,  Haruyasu Fukui

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A non-volatile semiconductor memory device, comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a first address inversion section for inverting or non-inverting the logical values of at least a specific bit of the input address signal and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal.

摘要翻译： 一种非易失性半导体存储器件，包括多个存储单元，每个存储单元包括多个存储器单元，用于识别外部输入的命令信号并输出​​识别信号的命令识别单元，用于产生用于执行的控制信号的内部控制单元 由识别信号指定的命令，地址控制部分，用于根据外部输入的地址信号，向包括要访问的多个存储体组的任意组合的存储区域产生内部地址信号;以及第一地址转换部分 用于反相或非反相输入地址信号的至少一个特定位的逻辑值，并将结果输入地址信号输出到地址控制部分。 基于控制信号和内部地址信号来访问预定的存储单元。

公开(公告)号：US06646947B2

公开(公告)日：2003-11-11

申请号：US10184133

申请日：2002-06-26

申请人： Haruyasu Fukui ,  Ken Sumitani ,  Yasumichi Mori

发明人： Haruyasu Fukui ,  Ken Sumitani ,  Yasumichi Mori

IPC分类号： G11C700

CPC分类号： G06F13/28

摘要： A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.

摘要翻译： 本发明的数据传输控制装置包括：用于识别输入控制命令的命令识别部分; 第一地址输出部分，用于基于输入的控制命令来控制数据传送地址的输出和存储顺序以及数据传送完成地址; 第一存储器地址存储部分，用于存储从第一地址输出部分输出的第一存储器阵列的数据传输开始地址; 第二存储器地址存储部分，用于存储从第一地址输出部分输出的第二存储器阵列的数据传输开始地址; 第三存储器地址存储部分，用于存储从第一地址输出部分输出的数据传输完成地址。

公开(公告)号：US06549475B2

公开(公告)日：2003-04-15

申请号：US10183857

申请日：2002-06-25

申请人： Ken Nakazawa ,  Ken Sumitani ,  Haruyasu Fukui ,  Yasumichi Mori

发明人： Ken Nakazawa ,  Ken Sumitani ,  Haruyasu Fukui ,  Yasumichi Mori

IPC分类号： G11C1604

CPC分类号： G11C7/22

摘要： A semiconductor memory device in which an input command controls an operation includes a command state machine for decoding the input command and outputting the decoding result; a plurality of status registers for storing state information of the semiconductor memory device; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of data to a second data bus. At least the first switching circuit, among the first and second switching circuits, is controlled by the decoding result output by the command state machine.

公开(公告)号：US06785185B2

公开(公告)日：2004-08-31

申请号：US10183742

申请日：2002-06-25

申请人： Ken Sumitani ,  Haruyasu Fukui

发明人： Ken Sumitani ,  Haruyasu Fukui

IPC分类号： G11C800

CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2245

摘要： A semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command while allowing a memory operation to at least one of the first and second memory sections. At least one of the first and second memory sections include a plurality of small memory regions, and the memory control section allows each of the plurality of small memory regions to be separately and simultaneously subjected to an access operation.

摘要翻译： 半导体存储器件包括包括多个存储器元件的第一和第二存储器部分，以及存储器控制部分，用于基于外部控制命令允许第一和第二存储器部分之间的数据传送操作，同时允许存储器操作至少一个 的第一和第二存储器部分。 第一和第二存储器区域中的至少一个包括多个小存储器区域，并且存储器控制部件允许多个小存储器区域中的每一个被单独地并且同时进行访问操作。

公开(公告)号：US06522581B2

公开(公告)日：2003-02-18

申请号：US09881315

申请日：2001-06-12

申请人： Hidekazu Takata ,  Haruyasu Fukui ,  Ken Sumitani

发明人： Hidekazu Takata ,  Haruyasu Fukui ,  Ken Sumitani

IPC分类号： G11C1604

CPC分类号： G11C11/005

摘要： A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device, a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.

摘要翻译： 半导体存储装置包括：多个第一存储器阵列，每个第一存储器阵列包括多个半导体存储元件，其中写入来自外部设备的数据，并且从该数据读出数据到外部设备;第二存储器阵列，其操作 与多个第一存储器阵列分开并且包括包括多个非易失性半导体存储元件的至少一个块; 以及数据传送部分，用于在多个第一存储器阵列和第二存储器阵列之间传送数据。

公开(公告)号：US06751716B2

公开(公告)日：2004-06-15

申请号：US09834519

申请日：2001-04-12

申请人： Ken Sumitani ,  Hidekazu Takata ,  Yuji Tanaka ,  Yasuyuki Aikawa

发明人： Ken Sumitani ,  Hidekazu Takata ,  Yuji Tanaka ,  Yasuyuki Aikawa

IPC分类号： G06F1200

CPC分类号： G06F21/79 ,  G06F12/1441 ,  G06F12/1466 ,  G11C8/20 ,  G11C16/22

摘要： A semiconductor storage device including: a memory having a memory space, a plurality of addresses of the memory space each having data stored therein; and a security circuit for controlling a security function which activates or deactivates at least a part of the memory space according to whether, in the case where an address input to the security-circuit matches at least one key-address included in the security circuit, data stored in the address in the memory space is manipulated under a condition equal to a predetermined condition or under a condition not equal to the predetermined condition.

摘要翻译： 一种半导体存储装置，包括：具有存储器空间的存储器，存储有数据的存储器空间的多个地址; 以及用于控制安全功能的安全电路，其根据在安全电路输入的地址与包括在安全电路中的至少一个密钥地址匹配的情况下，激活或去激活存储器空间的至少一部分， 存储在存储器空间中的地址中的数据在等于预定条件的条件下或在不等于预定条件的条件下被操纵。

公开(公告)号：US06493278B2

公开(公告)日：2002-12-10

申请号：US09882602

申请日：2001-06-15

申请人： Hidekazu Takata ,  Ken Sumitani

发明人： Hidekazu Takata ,  Ken Sumitani

IPC分类号： G11C700

CPC分类号： G11C7/24 ,  G11C16/22

摘要： A semiconductor device includes: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory. The operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.

摘要翻译： 半导体器件包括：具有用于记录数据的存储空间的存储器，所述存储器空间包括地址; 至少一个第一存储部分，用于存储请求访问存储器空间的地址的至少一部分和/或被请求写入存储器空间的数据; 以及用于至少部分地限制要对存储器执行的操作的操作限制电路。 操作限制电路基于存储在至少一个第一存储部分中的数据和/或地址的至少一部分来控制对存储器执行的操作的限制。

公开(公告)号：US08714764B2

公开(公告)日：2014-05-06

申请号：US13202368

申请日：2010-02-25

申请人： Atsushi Yamashita ,  Hiroyuki Nabesawa ,  Ken Sumitani ,  Manabu Yumoto ,  Manabu Onozaki

发明人： Atsushi Yamashita ,  Hiroyuki Nabesawa ,  Ken Sumitani ,  Manabu Yumoto ,  Manabu Onozaki

IPC分类号： G09F13/04 ,  G09F13/08 ,  F21S4/00 ,  F21V21/00

CPC分类号： G02F1/133609 ,  G02F1/133603 ,  G02F2001/133612

摘要： A light emitting module board which is compatible with a plurality of screen sizes and is used for a backlight apparatus of a liquid crystal display panel is provided. A light emitting module includes a first connector 15 and a second connector 16, each including a plurality of cathode terminals and at least one anode terminal, at each end of the board, and can be connected to another one to each other through the connectors in multi-level. A cathode wiring 14 for supplying a cathode control signal includes first cathode wirings which connect the cathode terminals of the first connector and light emitting bodies to supply a control signal to the light emitting bodies in the light emitting module, and second cathode wirings which connect the cathode terminals of the first and second connectors to supply a control signal to the light emitting bodies on a downstream light emitting module.

摘要翻译： 提供一种与多个屏幕尺寸兼容并用于液晶显示面板的背光装置的发光模块板。 发光模块包括第一连接器15和第二连接器16，每个包括多个阴极端子和至少一个阳极端子，在板的每个端部，并且可以通过连接器彼此连接到另一个 多层次 用于提供阴极控制信号的阴极布线14包括将第一连接器的阴极端子和发光体连接以向控制信号提供到发光模块中的发光体的第一阴极布线，以及将第 第一和第二连接器的阴极端子，以向下游发光模块上的发光体提供控制信号。

公开(公告)号：US07545683B2

公开(公告)日：2009-06-09

申请号：US11651455

申请日：2007-01-10

申请人： Ken Sumitani

发明人： Ken Sumitani

IPC分类号： G11C7/10

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C2216/14

摘要： A semiconductor memory device arranged for minimizing the duration of time required for conducting a batch verify action and thus speeding up a buffer write action is provided. The device which conducts a write action to memory cells in an address area, a batch verify action for collectively conducting verify action for a plurality of addresses, and repeats the batch verify action and the write action, comprises a detecting means for detecting whether or not each address contains an unwritten memory cell, and conducts a verify action at least at a part of the batch verify action excluding at least a part of addresses judged not to contain unwritten memory cells by the verify action at one or more cycles before.

摘要翻译： 提供一种半导体存储器件，其被设置用于使进行批次验证动作所需的持续时间最小化，从而加速缓冲器写入动作。 对地址区域中的存储单元进行写入动作的装置，对多个地址进行统一进行验证动作的批处理动作，重复批次验证动作和写入动作的检测装置，包括检测装置 每个地址包含未写入的存储器单元，并且至少在批量验证动作的一部分进行验证动作，除了在一个或多个周期之前通过验证动作判断为不包含未写入的存储器单元的地址的至少一部分。

公开(公告)号：US20070159895A1

公开(公告)日：2007-07-12

申请号：US11651455

申请日：2007-01-10

申请人： Ken Sumitani

发明人： Ken Sumitani

IPC分类号： G11C7/10

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C2216/14

摘要： A semiconductor memory device arranged for minimizing the duration of time required for conducting a batch verify action and thus speeding up a buffer write action is provided. The device which conducts a write action to memory cells in an address area, a batch verify action for collectively conducting verify action for a plurality of addresses, and repeats the batch verify action and the write action, comprises a detecting means for detecting whether or not each address contains an unwritten memory cell, and conducts a verify action at least at a part of the batch verify action excluding at least a part of addresses judged not to contain unwritten memory cells by the verify action at one or more cycles before.

摘要翻译： 提供一种半导体存储器件，其被设置用于使进行批次验证动作所需的持续时间最小化，从而加速缓冲器写入动作。 对地址区域中的存储单元进行写入动作的装置，对多个地址进行统一进行验证动作的批处理动作，重复批次验证动作和写入动作的检测装置，包括检测装置 每个地址包含未写入的存储器单元，并且至少在批量验证动作的一部分进行验证动作，除了在一个或多个周期之前通过验证动作判断为不包含未写入的存储器单元的地址的至少一部分。