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1.发明授权Executing variable length instructions stored within a plurality of discrete memory address regions 有权执行存储在多个离散存储器地址区域内的可变长度指令公开(公告)号：US07676652B2
公开(公告)日：2010-03-09
申请号：US10648293
申请日：2003-08-27
CPC分类号： G06F9/3816 , G06F9/30149 , G06F12/04
摘要： Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered. This execution is constrained by the setting of a single step flag which causes the hardware to only execute the single instruction which span the gap before returning control to a single step exception handler which can then restore program flow to the point in the following memory region after the variable length instruction which spanned the gap.
摘要翻译： 在支持执行可变长度指令的系统中，程序被存储在跨越两个这样的离散存储器区域之间的间隙的可变长度指令的离散存储器区域内。 当尝试跨越间隙的这种可变长度指令执行时，启动中止处理程序，其用于将其中一个存储器区域的端部与另一存储器区域的起始部分一起复制到单独的修正存储器区域 其中这些可以被级联，使得整个可变长度指令将出现在一个地方。 然后可以触发从固定存储区域中执行该可变长度指令。 该执行受到单步标志的设置的限制，这使得硬件仅在将控制返回到单步异常处理程序之前执行跨越间隙的单个指令，然后可以将程序流恢复到以下存储区域中的点 跨越差距的可变长度指令。
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公开(公告)号：US07426629B2
公开(公告)日：2008-09-16
申请号：US10527960
申请日：2003-10-06
CPC分类号： G06F9/30058 , G06F9/30189 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3875 , G06F21/71 , G06F21/75 , G06F21/755 , G06F2207/7219 , G06F2221/2123
摘要： A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not vary in dependence upon the data value being written or the previous data value.
摘要翻译： 数据处理系统具有这样的机制，即当数据值被存储在数据寄存器中时，另外的数据值存储在一个或多个另外的寄存器中，使得从高到低和从低到高的信号转换的总数量 不依赖于正在写入的数据值或先前的数据值而变化。
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公开(公告)号：US07313677B2
公开(公告)日：2007-12-25
申请号：US10527575
申请日：2003-10-06
CPC分类号： G06F9/30058 , G06F9/30189 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3875 , G06F21/71 , G06F21/75 , G06F21/755 , G06F2207/7219 , G06F2221/2123
摘要： Apparatus for processing data under control of data processing instructions specifying data processing operations, said apparatus comprising: a first execution mechanism operable to execute a first set of data processing instructions; a second execution mechanism operable to execute a second set of data processing instructions, said first set of data processing instructions overlapping with said second set of data processing instructions such that one or more data processing instructions are executable by either said first execution mechanism or said second execution mechanism; and an execution mechanism selector operable to pseudo randomly selected either said first execution mechanism or said second execution mechanism to execute one or more data processing instructions that are executable by either said first execution mechanism or said second execution mechanism.
摘要翻译： 用于在指定数据处理操作的数据处理指令的控制下处理数据的装置，所述装置包括：第一执行机构，可操作以执行第一组数据处理指令; 第二执行机构，其可操作以执行第二组数据处理指令，所述第一组数据处理指令与所述第二组数据处理指令重叠，使得一个或多个数据处理指令可由所述第一执行机构或所述第二执行机构执行 执行机制; 以及执行机构选择器，用于伪随机选择所述第一执行机构或所述第二执行机构，以执行可由所述第一执行机构或所述第二执行机构执行的一个或多个数据处理指令。
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公开(公告)号：US08738971B2
公开(公告)日：2014-05-27
申请号：US13313057
申请日：2011-12-07
IPC分类号： G06F11/00
CPC分类号： G06F11/0721 , G06F11/076 , G06F11/3024 , G06F11/3058
摘要： A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change. The data processing apparatus further comprises performance control circuitry configured to determine when the data processing apparatus is operating close to the operating region limits where an error rate is raised and in response to determining operation close to the operating region limits to modify a behavior of the data processing apparatus by at least one of: limiting speculative processing, and selecting timing insensitive processing paths and circuitry.
摘要翻译： 一种数据处理装置，被配置为在电压和频率操作区域中操作，所述电压和频率操作区域位于不存在错误的安全区域之外，但是在操作区域限制内，使得错误是罕见的。 数据处理装置包括：错误检测电路和错误恢复电路; 所述错误检测电路被配置为确定在所述处理装置中采样的信号是否在所述信号被采样之后并且在与所述采样相同的时钟周期期间发生的时间窗内改变，并且如果所述信号确实改变则发送信号。 数据处理装置还包括性能控制电路，其被配置为确定数据处理装置何时操作接近错误率提高的操作区域限制，并且响应于确定接近操作区域限制的操作来修改数据的行为 处理装置中的至少一个：限制推测处理，以及选择不敏感时序的处理路径和电路。
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5.发明申请DATA PROCESSING APPARATUS WITH AN EXECUTION PIPELINE AND ERROR RECOVERY UNIT AND METHOD OF OPERATING THE DATA PROCESSING APPARATUS 有权具有执行管线和错误恢复单元的数据处理装置及操作数据处理装置的方法公开(公告)号：US20130166952A1
公开(公告)日：2013-06-27
申请号：US13336432
申请日：2011-12-23
申请人： Guillaume Schon , Mélanie Emanuelle Lucie Teyssier , Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
发明人： Guillaume Schon , Mélanie Emanuelle Lucie Teyssier , Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
IPC分类号： G06F11/14
CPC分类号： G06F9/3865 , G06F9/3855 , G06F9/3861 , G06F11/0736 , G06F11/0757 , G06F11/1405 , G06F11/1497
摘要： A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.
摘要翻译： 数据处理装置以流水线执行阶段的顺序执行指令。 错误检测单元对与执行指令相关联的信号进行两次采样，并且如果样本不同则产生误差信号。 异常存储单元维护与发出到执行流水线的指令相对应的条目的年龄排序列表，并且可以标记条目以显示是否已经与该指令相关联地生成了错误信号。 定时器单元响应于产生误差信号以启动预定时间段的定时。 如果列表中的最旧的等待条目具有与其相关联地存储的所述错误标记，则错误恢复单元启动软管道冲洗过程，并且如果所述预定时间段过去则启动硬管道冲洗过程，所述硬冲洗程序包括将所述流水线重置为 预定状态。
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公开(公告)号：US07809930B2
公开(公告)日：2010-10-05
申请号：US11657134
申请日：2007-01-24
IPC分类号： G06F9/34
CPC分类号： G06F9/3842 , G06F9/30072 , G06F9/384
摘要： A register renaming unit has mapping control circuitry which serves to suppress unnecessary mapping operations in dependence upon a detected current state of the data processing system. One example of circumstances which can be detected from the current state and in which mapping can be suppressed and the existing mapping reused are that in respect of the existing physically mapped register there are no pending writes, no pending reads and no pending requirement for that physically mapped register to be preserved as a recovery register. Another example of a current state in which a mapping can be reused is adjacent program instructions having mutually exclusive condition codes and sharing a destination register such that only one of those adjacent instructions will ever be executed.
摘要翻译： 寄存器重命名单元具有映射控制电路，其用于根据检测到的数据处理系统的当前状态来抑制不必要的映射操作。 可以从当前状态检测并且可以抑制映射的情况的一个示例，并且现有的映射重用是对于现有的物理映射寄存器，没有待处理的写入，没有等待读取，并且没有对物理上的待决请求 映射寄存器作为恢复寄存器保存。 可以重用映射的当前状态的另一示例是具有互斥条件码并且共享目的地寄存器的相邻的程序指令，使得只有一个相邻指令将被执行。
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公开(公告)号：US09052909B2
公开(公告)日：2015-06-09
申请号：US13313053
申请日：2011-12-07
申请人： Frederic Claude Marie Piry , Luca Scalabrino , Guillaume Schon , Melanie Emanuelle Lucie Teyssier
发明人： Frederic Claude Marie Piry , Luca Scalabrino , Guillaume Schon , Melanie Emanuelle Lucie Teyssier
CPC分类号： G06F9/38 , G06F9/384 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/0772 , G06F11/0793 , G06F11/1407
摘要： A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.
摘要翻译： 具有处理流水线的数据处理装置，流水线包括异常控制电路和错误检测电路。 异常存储单元被配置为维护与发出到处理流水线的指令相对应的条目的年龄排序列表以供执行。 该单元被配置为与每个条目相关联地存储指示指令是异常指令的异常指示以及它是否已经产生异常以及指示指令是否已经产生错误的错误指示符。 所述装置被配置为在所述指令的处理已经到达已知所述指令是否将产生错误以及所述指令是否将产生异常的阶段时向所述异常存储单元指示指令被解析; 并且异常控制电路被配置为从异常存储单元中的列表中顺序地退出最旧的解析条目。
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公开(公告)号：US08640008B2
公开(公告)日：2014-01-28
申请号：US13336428
申请日：2011-12-23
IPC分类号： H03M13/00
CPC分类号： G06F11/1407 , G06F11/1497
摘要： A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.
摘要翻译： 数据处理装置具有错误检测单元，每个错误检测单元被配置为如果与指令的执行相关联的信号的第一和第二采样不同，则生成错误信号。 错误值产生电路产生一个错误值，显示任何错误检测单元是否产生了错误信号。 误差值稳定电路执行稳定程序，包括重新采样误差值以消除亚稳态。 错误恢复电路如果错误值被确认则启动指令的重新执行。 计数电路与错误值相关联地保持计数器值，当误差值被产生并且每当在到达误差值稳定电路之前重新采样误差值时递减，计数器值被设置为预定值。 如果在错误值到达故障值稳定电路之前计数器值为零，则误差值会绕过稳定程序。
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公开(公告)号：US20090282304A1
公开(公告)日：2009-11-12
申请号：US12149851
申请日：2008-05-08
CPC分类号： G06F11/3648
摘要： An apparatus for processing data includes diagnostic mechanisms for providing watch point and breakpoint functionality. Semaphores are associated with the watch points and are provided with hardware support within the diagnostic circuitry serving to monitor whether or not accesses to watch point data is being made in accordance with the permissions set up and noted in the semaphore data.
摘要翻译： 用于处理数据的装置包括用于提供观察点和断点功能的诊断机构。 信标与观察点相关联，并在诊断电路内提供硬件支持，用于监视是否根据在信号量数据中设置和记录的权限进行对观察点数据的访问。
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公开(公告)号：US20080177983A1
公开(公告)日：2008-07-24
申请号：US11657134
申请日：2007-01-24
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30072 , G06F9/384
摘要： A register renaming unit 8 has mapping control circuitry 24 which serves to suppress unnecessary mapping operations in dependence upon a detected current state of the data processing system 2. One example of circumstances which can be detected from the current state and in which mapping can be suppressed and the existing mapping reused are that in respect of the existing physically mapped register there are no pending writes, no pending reads and no pending requirement for that physically mapped register to be preserved as a recovery register. Another example of a current state in which a mapping can be reused is adjacent program instructions having mutually exclusive condition codes and sharing a destination register such that only one of those adjacent instructions will every be executed.
摘要翻译： 寄存器重命名单元8具有映射控制电路24，其用于根据检测到的数据处理系统2的当前状态来抑制不必要的映射操作。 可以从当前状态检测并且可以抑制映射的情况的一个示例，并且现有的映射重用是对于现有的物理映射寄存器，没有待处理的写入，没有等待读取，并且没有对物理上的待决请求 映射寄存器作为恢复寄存器保存。 可以重用映射的当前状态的另一个示例是具有互斥状态码并且共享目的地寄存器的相邻的程序指令，使得这些相邻指令中的仅一个将被执行。
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