公开(公告)号：US20100194456A1

公开(公告)日：2010-08-05

申请号：US12592753

申请日：2009-12-02

申请人： Hee Chai Kang ,  Kyeong Ho Ryu ,  Seong Ook Jung ,  Won Lee ,  Dong Hwan Lee ,  Alex Joo ,  Jong Ryun Choi

发明人： Hee Chai Kang ,  Kyeong Ho Ryu ,  Seong Ook Jung ,  Won Lee ,  Dong Hwan Lee ,  Alex Joo ,  Jong Ryun Choi

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/00006 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/07 ,  H03L7/0995 ,  H03L7/10

摘要： A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.

摘要翻译： 延迟锁定环控制包括在延迟线中的多个延迟块，从而产生具有通过将参考时钟信号的频率，精确相位延迟和恒定占空比相乘而获得的频率的多个时钟信号。 延迟锁定环路计算初始延迟值并将其应用于延迟块，从而防止谐波锁定并减少锁定时间。

公开(公告)号：US08049543B2

公开(公告)日：2011-11-01

申请号：US12592753

申请日：2009-12-02

申请人： Hee Chai Kang ,  Kyeong Ho Ryu ,  Seong Ook Jung ,  Won Lee ,  Dong Hwan Lee ,  Alex Joo ,  Jong-Ryun Choi

发明人： Hee Chai Kang ,  Kyeong Ho Ryu ,  Seong Ook Jung ,  Won Lee ,  Dong Hwan Lee ,  Alex Joo ,  Jong-Ryun Choi

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/00006 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/07 ,  H03L7/0995 ,  H03L7/10

摘要： A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.

摘要翻译： 延迟锁定环控制包括在延迟线中的多个延迟块，从而产生具有通过将参考时钟信号的频率，精确相位延迟和恒定占空比相乘而获得的频率的多个时钟信号。 延迟锁定环路计算初始延迟值并将其应用于延迟块，从而防止谐波锁定并减少锁定时间。