Duty cycle correction circuits having short locking times that are relatively insensitive to temperature changes
    5.
    发明授权
    Duty cycle correction circuits having short locking times that are relatively insensitive to temperature changes 有权
    具有对温度变化相对不敏感的短锁定时间的占空比校正电路

    公开(公告)号:US07990195B2

    公开(公告)日:2011-08-02

    申请号:US12603717

    申请日:2009-10-22

    IPC分类号: H03K3/017

    CPC分类号: H03K5/1565

    摘要: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.

    摘要翻译: 占空比校正电路包括占空比校正部分,其被配置为输出通过校正输入信号的占空比获得的校正信号,并输出通过延迟校正信号而获得的延迟信号;互补部分, 被配置为输出作为所述延迟信号的互补的互补信号,以及相位插值器,被配置为相互插补所述互补信号和所述校正信号。

    DUTY CYCLE CORRECTION CIRCUITS HAVING SHORT LOCKING TIMES THAT ARE RELATIVELY INSENSITIVE TO TEMPERATURE CHANGES
    6.
    发明申请
    DUTY CYCLE CORRECTION CIRCUITS HAVING SHORT LOCKING TIMES THAT ARE RELATIVELY INSENSITIVE TO TEMPERATURE CHANGES 有权
    具有相对温度变化敏感的短暂锁定时间的周期校正电路

    公开(公告)号:US20100097112A1

    公开(公告)日:2010-04-22

    申请号:US12603717

    申请日:2009-10-22

    IPC分类号: H03K3/017

    CPC分类号: H03K5/1565

    摘要: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.

    摘要翻译: 占空比校正电路包括占空比校正部分,其被配置为输出通过校正输入信号的占空比获得的校正信号,并输出通过延迟校正信号而获得的延迟信号;互补部分, 被配置为输出作为所述延迟信号的互补的互补信号,以及相位插值器,被配置为相互插补所述互补信号和所述校正信号。

    Duty control circuit and semiconductor device having the same
    7.
    发明申请
    Duty control circuit and semiconductor device having the same 有权
    占空比控制电路和具有相同功能的半导体器件

    公开(公告)号:US20100073059A1

    公开(公告)日:2010-03-25

    申请号:US12585680

    申请日:2009-09-22

    IPC分类号: H03K3/017

    CPC分类号: H03K5/1565 H03K2005/00058

    摘要: A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.

    摘要翻译: 一种占空比控制电路,包括连接到第一节点和第二节点的时钟输入单元,时钟输入单元通过第一节点接收输入时钟信号,并将第二节点的电压改变为第一电压电平和第二节点之一 响应于输入时钟信号的相应低和高逻辑电平的电压电平,连接到第二节点的转换控制器,所述转换控制器包括由相应控制信号控制的一个或多个开关,所述一个或多个开关提供第一 电压电平和第二电压电平响应于控制信号,使得第二节点处的信号的转换速率改变;以及时钟输出单元,时钟输出单元输出具有占空比的输出时钟信号 不一样。

    Digital DLL including skewed gate type duty correction circuit and duty correction method thereof
    8.
    发明授权
    Digital DLL including skewed gate type duty correction circuit and duty correction method thereof 有权
    数字DLL包括偏斜门型占空比校正电路及其占空比校正方法

    公开(公告)号:US08519758B2

    公开(公告)日:2013-08-27

    申请号:US13046073

    申请日:2011-03-11

    IPC分类号: H03L7/06 H03K5/04

    摘要: Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.

    摘要翻译: 提供了可以包括在数据处理装置中的延迟锁定环(DLL),并且可以包括这样的DLL的占空比校正电路和占空比校正方法。 占空比校正方法包括:在时钟的第一次转换时对输出时钟进行二次转换,对输出时钟的第一次转换进行占空比校正的时钟采样,以检测占空比的误差,并执行占空比 根据检测到的占空比误差,使用偏斜栅极链进行校正。

    Duty control circuit and semiconductor device having the same
    9.
    发明授权
    Duty control circuit and semiconductor device having the same 有权
    占空比控制电路和具有相同功能的半导体器件

    公开(公告)号:US07994835B2

    公开(公告)日:2011-08-09

    申请号:US12585680

    申请日:2009-09-22

    IPC分类号: H03K3/017

    CPC分类号: H03K5/1565 H03K2005/00058

    摘要: A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.

    摘要翻译: 一种占空比控制电路,包括连接到第一节点和第二节点的时钟输入单元,时钟输入单元通过第一节点接收输入时钟信号,并将第二节点的电压改变为第一电压电平和第二节点之一 响应于输入时钟信号的相应低和高逻辑电平的电压电平,连接到第二节点的转换控制器,所述转换控制器包括由相应控制信号控制的一个或多个开关,所述一个或多个开关提供第一 电压电平和第二电压电平响应于控制信号,使得第二节点处的信号的转换速率改变;以及时钟输出单元,时钟输出单元输出具有占空比的输出时钟信号 不一样。

    Sensor for measuring liquid contaminants in a semiconductor wafer fabrication process
    10.
    发明授权
    Sensor for measuring liquid contaminants in a semiconductor wafer fabrication process 有权
    用于在半导体晶圆制造工艺中测量液体污染物的传感器

    公开(公告)号:US07696538B2

    公开(公告)日:2010-04-13

    申请号:US11371650

    申请日:2006-03-09

    申请人: Won Lee Evan E Patton

    发明人: Won Lee Evan E Patton

    IPC分类号: H01L29/84

    摘要: Liquid detection sensors are attached to both sides of a robotic arm end effector of a semiconductor wafer process system. The sensor mechanism or probe is situated on the front side and backside of the end effector, designed with electrical lines that are traced onto a polyester base material. The electrical lines are positioned in a serpentine formation. The high conductance of the sulfuric acid in the copper sulfate solution acts as the conductor between the traced lines. When the conductive liquid comes in contact with the traced lines, the lines short and the sensor activates or turns on.

    摘要翻译: 液体检测传感器连接到半导体晶片处理系统的机器人臂端部执行器的两侧。 传感器机构或探头位于末端执行器的前侧和后侧,设计有跟踪在聚酯基材上的电线。 电线定位在蛇形结构中。 硫酸铜溶液中硫酸的高电导作用在跟踪线之间的导体。 当导电液体与跟踪线接触时,线路短路,传感器激活或打开。