公开(公告)号：US20080061371A1

公开(公告)日：2008-03-13

申请号：US11930265

申请日：2007-10-31

申请人： Hee-soo KANG ,  Dong-gun PARK ,  Choong-ho LEE ,  Hye-Jin CHO ,  Young-Joon AHN

发明人： Hee-soo KANG ,  Dong-gun PARK ,  Choong-ho LEE ,  Hye-Jin CHO ,  Young-Joon AHN

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4908 ,  H01L29/66787 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.

摘要翻译： 一方面，提供具有单元区域和外围电路区域的半导体基板，并且在半导体基板的单元区域和外围电路区域上形成掩模层。 通过在掩模层中形成第一开口以暴露半导体衬底的单元区域中的第一栅极区域，然后使用镶嵌工艺在第一开口中形成FinFET栅电极来制造FinFET栅极。 通过在掩模层中形成第二开口以暴露半导体衬底的外围电路区域中的第二栅极区域，然后使用镶嵌工艺在第二开口中形成MOSFET栅电极来制造MOSFET栅极。

公开(公告)号：US20110310665A1

公开(公告)日：2011-12-22

申请号：US13218715

申请日：2011-08-26

申请人： Jong-Ho LIM ,  Choong-Ho LEE ,  Hye-Jin CHO

发明人： Jong-Ho LIM ,  Choong-Ho LEE ,  Hye-Jin CHO

IPC分类号： G11C16/04

CPC分类号： H01L27/11551

摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件包括多个堆叠的半导体层和形成在多个半导体层中的每一个上并且串联连接的多个存储单元晶体管。 配置在不同的半导体层上的存储单元晶体管被串联连接以包括在多个半导体层中形成电流路径的一个单元串，串联连接到单元串的一个边缘部分的第一选择晶体管和串联连接到单元串的第二选择晶体管 单元格串的其他边缘部分。

公开(公告)号：US20090286004A1

公开(公告)日：2009-11-19

申请号：US12346081

申请日：2008-12-30

申请人： Sung-Il OH ,  Jae-Woo JOUNG ,  Hyun-Chul JUNG ,  Sung-Nam CHO ,  In-Young KIM ,  Young-Ah SONG ,  Su-Hwan CHO ,  Hye-Jin CHO

发明人： Sung-Il OH ,  Jae-Woo JOUNG ,  Hyun-Chul JUNG ,  Sung-Nam CHO ,  In-Young KIM ,  Young-Ah SONG ,  Su-Hwan CHO ,  Hye-Jin CHO

IPC分类号： B05D5/12 ,  B32B7/12

CPC分类号： H05K3/1258 ,  H05K3/125 ,  H05K2201/09909 ,  H05K2203/013 ,  H05K2203/1173

摘要： Disclosed are methods of forming a printed circuit pattern and forming a guide, and a guide-forming ink. The method of forming a printed circuit pattern in accordance with the present invention includes forming a guide by using guide-forming ink having a slip property, curing the formed guide by in-situ UV, and forming a printed circuit pattern on the inside of the cured guide by using metal ink.

摘要翻译： 公开了形成印刷电路图案和形成引导件的方法以及引导成形油墨。 根据本发明的形成印刷电路图案的方法包括通过使用具有滑动性的引导成形油墨来形成引导件，通过原位UV固化所形成的引导件，并且在内部形成印刷电路图案 通过使用金属油墨固化引导。

公开(公告)号：US20080036001A1

公开(公告)日：2008-02-14

申请号：US11832589

申请日：2007-08-01

申请人： Eun-Jung YUN ,  Hye-Jin CHO ,  Dong-Won KIM ,  Sung-Min KIM

发明人： Eun-Jung YUN ,  Hye-Jin CHO ,  Dong-Won KIM ,  Sung-Min KIM

IPC分类号： H01L27/01 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

摘要翻译： 一种具有场效应晶体管的半导体器件及其制造方法。 通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。 原位掺杂的外延图案贯穿整个杂质浓度。 因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。 结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。