公开(公告)号：US20050048732A1

公开(公告)日：2005-03-03

申请号：US10604912

申请日：2003-08-26

申请人： Heemyoung Park ,  Paul Agnello ,  Percy Gilbert ,  Byoung Lee ,  Patricia O'Neil ,  Ghavam Shahidi ,  Jeffrey Welser

发明人： Heemyoung Park ,  Paul Agnello ,  Percy Gilbert ,  Byoung Lee ,  Patricia O'Neil ,  Ghavam Shahidi ,  Jeffrey Welser

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

摘要： Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height that forms a laminated structure having a substrate, a gate conductor above the substrate, and at least one sacrificial layer above the gate conductor. The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions adjacent the gate stack, and removes the spacers and the sacrificial layer.

摘要翻译： 公开了一种形成具有降低的栅极高度的集成电路晶体管的方法和系统，其形成具有衬底的层压结构，在衬底上方的栅极导体以及栅极导体上方的至少一个牺牲层。 该过程将层叠结构图案化为从衬底延伸的至少一个栅极堆叠，形成邻近栅极叠层的间隔物，掺杂不被间隔物保护的衬底的区域，以形成邻近栅堆叠的源区和漏区， 和牺牲层。

公开(公告)号：US06436823B1

公开(公告)日：2002-08-20

申请号：US09679738

申请日：2000-10-05

申请人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

发明人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L2221/1078

摘要： A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

摘要翻译： 提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法，而不形成含有Ti，Co和Si的厚非晶层以及形成的结构。 在该方法中，在金属硅化物层的顶部沉积Ti层之后，进行双相退火工艺，其中在不高于500℃的温度下在成形气体（或氨）中进行低温退火。 首先进行少于2小时，然后在不低于500℃的第二温度下在含氮气体（或氨）中进行低温退火2小时以形成TiN层。 本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题，并导致由于体积膨胀引起的衬管故障 无定形材料。 通过本发明方法形成的非晶材料层的最大厚度小于5nm，这使线路故障问题最小化。