公开(公告)号：US20080296706A1

公开(公告)日：2008-12-04

申请号：US12175549

申请日：2008-07-18

申请人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

发明人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134

摘要： A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.

摘要翻译： 一个结构。 该结构可以包括基本上不含一钴硅酸钴的二硅化钴层，并且在二硅化钴层上基本上没有钛氧化物的桁条。 该结构可以包括：衬底，其包括：绝缘栅场效应晶体管（FET），其包括源极，漏极和栅极; 在源极上的第二层二硅化钴，所述第一层基本上不含有一氧化硅钴，并且所述第一层在其上基本上不具有钛氧化物的桁条; 漏极上的第二层二硅化锡，所述第二层基本上不具有在其上的钛氧化物基本上没有棱的钴单硅化物; 和在栅极上的第二层二硅化锡，所述第三层基本上不含有一氧化硅钴，并且在其上基本上没有钛氧化物的桁条。

公开(公告)号：US20050048732A1

公开(公告)日：2005-03-03

申请号：US10604912

申请日：2003-08-26

申请人： Heemyoung Park ,  Paul Agnello ,  Percy Gilbert ,  Byoung Lee ,  Patricia O'Neil ,  Ghavam Shahidi ,  Jeffrey Welser

发明人： Heemyoung Park ,  Paul Agnello ,  Percy Gilbert ,  Byoung Lee ,  Patricia O'Neil ,  Ghavam Shahidi ,  Jeffrey Welser

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

摘要： Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height that forms a laminated structure having a substrate, a gate conductor above the substrate, and at least one sacrificial layer above the gate conductor. The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions adjacent the gate stack, and removes the spacers and the sacrificial layer.

摘要翻译： 公开了一种形成具有降低的栅极高度的集成电路晶体管的方法和系统，其形成具有衬底的层压结构，在衬底上方的栅极导体以及栅极导体上方的至少一个牺牲层。 该过程将层叠结构图案化为从衬底延伸的至少一个栅极堆叠，形成邻近栅极叠层的间隔物，掺杂不被间隔物保护的衬底的区域，以形成邻近栅堆叠的源区和漏区， 和牺牲层。

公开(公告)号：US07696586B2

公开(公告)日：2010-04-13

申请号：US12175549

申请日：2008-07-18

申请人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

发明人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134

摘要： A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.

摘要翻译： 一个结构。 该结构可以包括基本上不含一钴硅酸钴的二硅化钴层，并且在二硅化钴层上基本上没有钛氧化物的桁条。 该结构可以包括：衬底，其包括：绝缘栅场效应晶体管（FET），其包括源极，漏极和栅极; 在源极上的第二层二硅化钴，所述第一层基本上不含有一氧化硅钴，并且所述第一层在其上基本上不具有钛氧化物的桁条; 漏极上的第二层二硅化锡，所述第二层基本上不具有在其上的钛氧化物基本上没有棱的钴单硅化物; 和在栅极上的第二层二硅化锡，所述第三层基本上不含有一氧化硅钴，并且在其上基本上没有钛氧化物的桁条。

公开(公告)号：US20050287798A1

公开(公告)日：2005-12-29

申请号：US10710227

申请日：2004-06-28

申请人： Paul Agnello ,  Rajeev Malik ,  K. Muller

发明人： Paul Agnello ,  Rajeev Malik ,  K. Muller

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

摘要翻译： 公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。 本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。 轴承表面防止随后填充高纵横比区域的层间电介质的空化。

公开(公告)号：US20050040465A1

公开(公告)日：2005-02-24

申请号：US10952286

申请日：2004-09-28

申请人： Heemyong Park ,  Byoung Lee ,  Paul Agnello ,  Dominic Schepis ,  Ghavam Shahidi

发明人： Heemyong Park ,  Byoung Lee ,  Paul Agnello ,  Dominic Schepis ,  Ghavam Shahidi

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅电介质; 在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 以及加热所述器件以从所述注入层和所述SOI晶片形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于所述STI区域之下。

公开(公告)号：US06335294B1

公开(公告)日：2002-01-01

申请号：US09296338

申请日：1999-04-22

申请人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

发明人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

IPC分类号： H01L2100

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134

摘要： A method for removing a formation of oxide of titanium that is generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65° C. combined with a 3 minute period of application.

摘要翻译： 作为在绝缘栅场效应晶体管（FET）内形成二硅化钴的工序的副产物而生成的钛的氧化物的形成的方法。 该方法在规定的温度下向化学试剂施加化学试剂，并且在预定时间内，对于除去形成所需的预定时间，其中试剂不与二硅化钴发生化学反应。 实现这一任务的试剂包括水（H 2 O），氢氧化铵（NH 4 OH）和过氧化氢（H 2 O 2），其中NH 4 OH和H 2 O 2各自占总试剂体积的约4％。 有效温度为65°C，加上3分钟的使用时间。

公开(公告)号：US07411258B2

公开(公告)日：2008-08-12

申请号：US09939895

申请日：2001-08-27

申请人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

发明人： David Paul Agnello ,  Mary Conroy Bushey ,  Donna K. Johnson ,  Jerome Brett Lasky ,  Peter James Lindgren ,  Kirk David Peterson

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134

摘要： A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of cobalt monosilicide, with substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may alternatively comprise a layer of cobalt disilicide, a patch of an oxide of titanium, and a reagent in contact with the patch at a temperature and for a period of time. The layer is substantially free of cobalt monosilicide. The patch is on the layer of cobalt disilicide. The reagent is adapted to remove the patch within the period of time. The reagent does not chemically react with the layer of cobalt disilicide, and the reagent comprises water, ammonium hydroxide, and hydrogen peroxide.

摘要翻译： 涉及在绝缘栅场效应晶体管（FET）中除去作为形成二硅化钴的工艺的副产物的钛的氧化物的结构。 该结构可以包含基本上不含一钴硅酸钴的二硅化钴层，在二硅化钴层上基本上没有钛氧化物的桁条。 该结构可以可选地包括一层二硅化钴，一块钛的氧化物和在该温度和一段时间内与该贴片接触的试剂。 该层基本上不含一次硅化钴。 贴片在二硅化钴层上。 试剂适于在一段时间内除去贴剂。 试剂不与二硅化钴层发生化学反应，试剂包括水，氢氧化铵和过氧化氢。

公开(公告)号：US20070026617A1

公开(公告)日：2007-02-01

申请号：US11495518

申请日：2006-07-31

申请人： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

发明人： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L21/20 ,  H01L21/44

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：US20060030133A1

公开(公告)日：2006-02-09

申请号：US11208359

申请日：2005-08-19

申请人： Paul Agnello ,  Stephen Bedell ,  Robert Dennard ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

发明人： Paul Agnello ,  Stephen Bedell ,  Robert Dennard ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC分类号： H01L21/20 ,  H01L33/00 ,  H01L21/36

CPC分类号： H01L21/324 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66893 ,  H01L29/78603

摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

摘要翻译： 提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。 所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。 将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。 在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

公开(公告)号：US20050001216A1

公开(公告)日：2005-01-06

申请号：US10867772

申请日：2004-06-16

申请人： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

发明人： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

摘要翻译： 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。