公开(公告)号：US07259587B1

公开(公告)日：2007-08-21

申请号：US11081861

申请日：2005-03-15

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

IPC分类号： H03K19/177 ,  H01L25/00

CPC分类号： H01L25/065 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11898 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/17796 ,  H01L2924/00014 ,  H01L2924/00

摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.

公开(公告)号：US07573296B2

公开(公告)日：2009-08-11

申请号：US11082225

申请日：2005-03-15

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： G06F7/506 ,  G06F2207/3868 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. Each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable routing interconnect circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any routing circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular routing circuit in any interior tile and any circuit that provides an input of the particular routing circuit.

摘要翻译： 一些实施例提供了包括若干可配置瓦片的可配置IC。 可配置瓦片包括可配置瓦片布置内部的若干内部瓦片。 该布置具有限定布置的外部边界的几个边。 每个可配置内部瓦片包括一组可配置逻辑电路和一组可配置的路由互连电路，用于在可配置逻辑电路之间路由信号。 每个内部瓦片中的一组可配置路由互连电路具有由可配置IC中的一组不对称位置提供的一组输入。 任何内部瓦片中的任何路线电路与瓦片布置的任何边界限定侧之间的任何距离大于任何内部瓦片中的任何特定路由电路与提供特定路由电路的输入的任何电路之间的任何距离。

公开(公告)号：US07518402B2

公开(公告)日：2009-04-14

申请号：US11775218

申请日：2007-07-09

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

IPC分类号： H03K19/177

CPC分类号： H01L25/065 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11898 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/17796 ,  H01L2924/00014 ,  H01L2924/00

摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.

公开(公告)号：US07839166B2

公开(公告)日：2010-11-23

申请号：US11856214

申请日：2007-09-17

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H03K19/17736 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00

摘要： Some embodiments provide an integrated circuit that includes several groups of circuits, each group of circuits includes a set of configurable logic circuits. The integrated circuit has at least one direct connection, without any intervening interconnect circuits, that connects an output of a configurable logic circuit in one group of circuits to another circuit in another group of circuits that does not neighbor the first group of circuits and that is not aligned with the first group of circuits. In some embodiments, the direct connection has intervening buffer circuits, but no other intervening circuits.

摘要翻译： 一些实施例提供了包括几组电路的集成电路，每组电路包括一组可配置的逻辑电路。 集成电路具有至少一个直接连接，没有任何中间互连电路，其将一组电路中的可配置逻辑电路的输出连接到不与第一组电路相邻的另一组电路中的另一电路， 不与第一组电路对齐。 在一些实施例中，直接连接具有中间缓冲电路，但没有其他中间电路。

公开(公告)号：US07576564B2

公开(公告)日：2009-08-18

申请号：US11868959

申请日：2007-10-08

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

摘要翻译： 一些实施例提供了一种可配置集成电路（“IC”），其包括以瓦片排列方式布置的多个可配置瓦片。 每个可配置的瓦片具有一组可配置逻辑电路和一组用于在可配置逻辑电路之间路由信号的可配置路由电路。 第一瓦片的至少第一路由电路具有与第二瓦片的第二电路的至少一个直接连接，第二瓦片不邻近第一瓦片，并且不与水平或垂直对准在瓦片布置中的第一瓦片。

公开(公告)号：US07295037B2

公开(公告)日：2007-11-13

申请号：US11082193

申请日：2005-03-15

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

摘要翻译： 一些实施例提供了一种可配置集成电路（“IC”），其包括以瓦片排列方式布置的多个可配置瓦片。 每个可配置的瓦片具有一组可配置逻辑电路和一组用于在可配置逻辑电路之间路由信号的可配置路由电路。 第一瓦片的至少第一路由电路具有与第二瓦片的第二电路的至少一个直接连接，第二瓦片不邻近第一瓦片，并且不与水平或垂直对准在瓦片布置中的第一瓦片。

公开(公告)号：US07282950B1

公开(公告)日：2007-10-16

申请号：US11082228

申请日：2005-03-15

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H03K19/17736 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00

摘要： A configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

摘要翻译： 一种可配置的集成电路（“IC”），其包括以瓦片布置布置的多个可配置瓦片。 每个可配置的瓦片具有一组可配置逻辑电路和一组用于在可配置逻辑电路之间路由信号的可配置路由电路。 在一些实施例中，第一瓦片的至少第一逻辑电路具有与第二瓦片的第二电路的至少一个直接连接，第二瓦片不与第一瓦片相邻，并且不与水平或垂直对准在瓦片中的第一瓦片 安排。

公开(公告)号：US07962705B2

公开(公告)日：2011-06-14

申请号：US12729227

申请日：2010-03-22

申请人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

发明人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

IPC分类号： G06F9/315

CPC分类号： H03K19/17736 ,  H03K19/1776

摘要： Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

摘要翻译： 一些实施例提供了一种呈现比物理存储器更窄和更深的虚拟存储器的方法。 该方法接收包括一组实际存储器地址位和一组虚拟存储器位置位的存储器地址位置。 该方法使用实际存储器地址位从物理存储器中检索原始存储器字。 该方法通过使用桶形移位器将原始存储器字移动由虚拟存储器位置位确定的量，创建移位的存储器字。 该方法读取移位的存储器字的一部分。

公开(公告)号：US07595655B2

公开(公告)日：2009-09-29

申请号：US11769686

申请日：2007-06-27

申请人： Brad Hutchings ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave

发明人： Brad Hutchings ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave

IPC分类号： H03K19/00 ,  G06F17/50

CPC分类号： H03K19/17764 ,  H03K19/17736

摘要： Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between the configurable logic circuits, and a network for monitoring data. In some embodiments a method uses at least a subset of the configurable logic circuits and a first subset of the configurable routing circuits to implement a user design circuit on the configurable IC. The method uses a second subset of the configurable routing circuits to pass signals to the network.

摘要翻译： 一些实施例提供可配置集成电路（IC）。 IC具有用于执行逻辑操作的可配置逻辑电路，用于在可配置逻辑电路之间路由信号的可配置路由电路以及用于监视数据的网络。 在一些实施例中，一种方法使用可配置逻辑电路的至少一个子集和可配置路由电路的第一子集来实现可配置IC上的用户设计电路。 该方法使用可配置路由电路的第二子集将信号传递到网络。

公开(公告)号：US07307449B1

公开(公告)日：2007-12-11

申请号：US11269168

申请日：2005-11-07

申请人： Jason Redgrave ,  Brad Hutchings ,  Herman Schmit ,  Steven Teig

发明人： Jason Redgrave ,  Brad Hutchings ,  Herman Schmit ,  Steven Teig

IPC分类号： H03K19/173

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17796

摘要： Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

摘要翻译： 本发明的一些实施例提供了可配置的集成电路（“IC”）。 该IC包括用于接收配置数据并且可配置地基于配置数据执行一组操作的多个可配置电路。 它还包括几个混合电路。 每个特定的混合电路可以互换地作为可配置IC中的逻辑电路或互连电路执行。