公开(公告)号：US20210035640A1

公开(公告)日：2021-02-04

申请号：US16526455

申请日：2019-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： CAN LI ,  CATHERINE GRAVES ,  JOHN PAUL STRACHAN

IPC: G11C15/04

Abstract: A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.

公开(公告)号：US20230246655A1

公开(公告)日：2023-08-03

申请号：US17580146

申请日：2022-01-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： JOHN PAUL STRACHAN ,  CAN LI ,  CATHERINE GRAVES

IPC: H03M13/15 ,  H03M13/11 ,  H03M13/00 ,  G11C27/00 ,  G11C13/00

CPC classification number: H03M13/1575 ,  G11C13/004 ,  G11C13/0069 ,  G11C27/005 ,  H03M13/1177 ,  H03M13/6597

Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other nonvolatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.

公开(公告)号：US20220351794A1

公开(公告)日：2022-11-03

申请号：US17245540

申请日：2021-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： CATHERINE GRAVES ,  CAN LI ,  JOHN PAUL STRACHAN

IPC: G11C27/00 ,  G11C15/04

Abstract: An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.

公开(公告)号：US20220138204A1

公开(公告)日：2022-05-05

申请号：US17085805

申请日：2020-10-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： CATHERINE GRAVES ,  CAN LI ,  JOHN PAUL STRACHAN ,  DEJAN S. MILOJICIC ,  KIMBERLY KEETON

IPC: G06F16/2455 ,  G06F16/22 ,  G06F16/901 ,  G06F1/3296 ,  G06F1/3206 ,  G11C27/00 ,  G11C13/00

Abstract: Encoding of domain logic rules in an analog content addressable memory (aCAM) is disclosed. By encoding domain logic in an aCAM, rapid and flexible search capabilities are enabled, including the capability to search ranges of analog values, fuzzy match capabilities, and optimized parameter search capabilities. This is achieved with low latency by using only a small number of clock cycles at low power. A domain logic ruleset may be represented using various data structures such as decision trees, directed graphs, or the like. These representations can be converted to a table of values, where each table column can be directly mapped to a corresponding row of the aCAM.