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公开(公告)号：US12101875B2
公开(公告)日：2024-09-24
申请号：US17362734
申请日：2021-06-29
发明人： David P. Kopp , Karl J. Bois , Steven J. Martin
CPC分类号： H05K1/0233 , G11C5/04 , H01P1/203 , H03H7/38 , H05K3/0005 , H05K2201/10159
摘要： One aspect provides a printed circuit board (PCB). The PCB includes a transmission line to transmit signals of a desired frequency, a first stub coupled to the transmission line at a first location, and a second stub coupled to the transmission line at a second location. The first stub is to filter out signals of a first frequency, the second stub is to filter out signals of a second frequency, and the first and second stubs are positioned such that an insertion loss of the transmitted signals of the desired frequency is substantially minimized.
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公开(公告)号：US20220139791A1
公开(公告)日：2022-05-05
申请号：US17084375
申请日：2020-10-29
发明人： Melvin K. Benedict , Karl J. Bois
IPC分类号： H01L21/66 , H01L21/768
摘要： Systems and assemblies are provided for transposition channel routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. The techniques involve “transposition” of a signal line pair on the PCB, reduces effect coupling coefficients for individual aggressor signals, thereby reducing the crosstalk. Transposition channel routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. The PCB can include an array of contact pads, a plurality of signal line pairs that include an escape route. One or more transposition junctions disposed within the escape route can route a signal line pair from a first routing channel in the escape route into a second routing channel in the escape route.
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公开(公告)号：US11281833B1
公开(公告)日：2022-03-22
申请号：US17084343
申请日：2020-10-29
发明人： Melvin K. Benedict , Karl J. Bois
IPC分类号： G06F30/392 , G06F30/347 , G06F30/398 , G06F30/394
摘要： Systems and assemblies are provided for exchanged signal routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. Exchanged signal routing techniques involve “exchanging” the signal routing lanes on the PCB, which reduces coupled signal amplitude and phase relationship. Exchanged signal routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. A printed circuit board (PCB) can include an array of contact pads, a plurality of signal lines that include an escape route. One or more exchange junctions disposed within the escape route can route a first signal line of a first routing channel in the escape route into a second routing channel in the escape route.
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公开(公告)号：US10178761B2
公开(公告)日：2019-01-08
申请号：US15141131
申请日：2016-04-28
发明人： Karl J. Bois , Benjamin Toby
摘要： A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer, and as an antenna radiates the EMI propagated by the strip lines along the signaling layer outwards from the circuit board. A defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines to minimize the EMI that the element radiates outwards as the antenna.
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公开(公告)号：US20170318665A1
公开(公告)日：2017-11-02
申请号：US15141131
申请日：2016-04-28
发明人： Karl J. Bois , Benjamin Toby
CPC分类号： H05K1/0245 , H05K1/0225 , H05K1/0298 , H05K1/115
摘要： A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer, and as an antenna radiates the EMI propagated by the strip lines along the signaling layer outwards from the circuit board. A defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines to minimize the EMI that the element radiates outwards as the antenna.
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公开(公告)号：US20190239338A1
公开(公告)日：2019-08-01
申请号：US15882649
申请日：2018-01-29
发明人： Melvin K. Benedict , Karl J. Bois
摘要： An electronic device includes a printed circuit board. The printed circuit board includes a plurality of different signaling planes and a plurality of different reference planes. A single ended via interconnects the plurality of different signaling planes. A return via interconnects the plurality of different reference planes. The electronic device includes a shared void that includes the single ended via and the return via.
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7.发明申请公开(公告)号：US20190021164A1
公开(公告)日：2019-01-17
申请号：US15650223
申请日：2017-07-14
发明人： Karl J. Bois , Elene Chobanyan , Benjamin Toby
摘要： A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer. A void of a defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines. A resistive material of the defected ground structure along a perimeter of the void improves suppression of the EMI propagated by the strip lines, via the resistive material absorbing the EMI.
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公开(公告)号：US09971864B2
公开(公告)日：2018-05-15
申请号：US15217284
申请日：2016-07-22
发明人： Karl J. Bois , Elene Chobanyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A system may include an input engine and a symmetry verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a particular net in the electronic circuit design. The a symmetry verification engine may identify a pair of differential signal vias in the electronic circuit design corresponding to the particular net and determine a verification area surrounding the pair of differential signal vias. The symmetry verification engine may also verify that a particular ground via within the verification area satisfies symmetry criteria with respect to the pair of differential signal vias.
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公开(公告)号：US20180089358A1
公开(公告)日：2018-03-29
申请号：US15280906
申请日：2016-09-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/78
摘要： Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.
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公开(公告)号：US20180025107A1
公开(公告)日：2018-01-25
申请号：US15217284
申请日：2016-07-22
发明人： Karl J. Bois , Elene Chobanyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A system may include an input engine and a symmetry verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a particular net in the electronic circuit design. The a symmetry verification engine may identify a pair of differential signal vias in the electronic circuit design corresponding to the particular net and determine a verification area surrounding the pair of differential signal vias. The symmetry verification engine may also verify that a particular ground via within the verification area satisfies symmetry criteria with respect to the pair of differential signal vias.
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