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    Programming method of nonvolatile semiconductor memory device
    7.
    发明授权
    Programming method of nonvolatile semiconductor memory device 有权

    公开(公告)号：US06636437B2

    公开(公告)日：2003-10-21

    申请号：US10260407

    申请日：2002-10-01

    申请人： Naoki Kobayashi ,  Hideaki Kurata ,  Katsutaka Kimura ,  Takashi Kobayashi ,  Shunichi Saeki

    发明人： Naoki Kobayashi ,  Hideaki Kurata ,  Katsutaka Kimura ,  Takashi Kobayashi ,  Shunichi Saeki

    IPC分类号： G11C1604

    CPC分类号： G11C11/5628

    摘要： In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.

    Nonvolatile semiconductor memory device
    8.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US06243290B1

    公开(公告)日：2001-06-05

    申请号：US09645878

    申请日：2000-08-25

    申请人： Hideaki Kurata ,  Naoki Kobayashi ,  Takashi Kobayashi ,  Katsutaka Kimura ,  Hitoshi Kume ,  Shunichi Saeki

    发明人： Hideaki Kurata ,  Naoki Kobayashi ,  Takashi Kobayashi ,  Katsutaka Kimura ,  Hitoshi Kume ,  Shunichi Saeki

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/32 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5623 ,  G11C2211/5624 ,  G11C2211/5642

    摘要： The present invention provides a nonvolatile semiconductor memory device for multilevel data storage that simultaneously carries out programming of multilevel data and subsequent verification at a high programming throughput. For this purpose, the present device includes a circuit 6 to hold programming data when programming is executed, a circuit 7 to generate timing signals to set up level-specific phases of verifying multilevel programming data during a verification period, a circuit 2 to increase stepwise the selected word line voltage during verification in accordance with the above timing signals, a circuit 4 to select target memory cells 1 for verification, depending on the data retrieved from the latch in accordance with the above timing signals, and verify whether the selected memory cells have been programmed on threshold voltage level, according to the energized or de-energized state thereof, and a circuit 5 to supply programming bias to the bit line to program data into insufficiently programmed memory cells, according to the verify results.

    摘要翻译： 本发明提供了一种用于多级数据存储的非易失性半导体存储器件，其以高编程吞吐量同时执行多级数据的编程和后续验证。为此，本设备包括：当执行编程时保存编程数据的电路6， 电路7，用于产生定时信号，以在验证期间建立验证多电平编程数据的电平特定相位;电路2，根据上述定时信号在校验期间逐步增加所选择的字线电压;电路4，用于选择 取决于根据上述定时信号从锁存器检索的数据，并且根据其通电或去激励状态来验证所选择的存储器单元是否已经被设置在阈值电压电平上，以及 一个向位线提供编程偏置以将数据编程为不足的电路5 根据验证结果，编程好的内存单元。