公开(公告)号：US20070176236A1

公开(公告)日：2007-08-02

申请号：US11649170

申请日：2007-01-03

申请人： Hideaki Oka ,  Kei Kanemoto

发明人： Hideaki Oka ,  Kei Kanemoto

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor device includes a semiconductor layer formed by epitaxial growth in a first region which is obtained by etching a semiconductor substrate to a predetermined depth, a surface of the semiconductor layer having a same height from the bottom of the semiconductor substrate as a height of a surface of the semiconductor substrate, a buried insulating layer buried between the semiconductor substrate and the semiconductor layer and an element isolation region separating each element region in the semiconductor layer and isolating the semiconductor layer from the semiconductor substrate in plan.

摘要翻译： 半导体器件包括通过在通过将半导体衬底蚀刻到预定深度而获得的第一区域中外延生长形成的半导体层，半导体层的与半导体衬底的底部相同高度的表面作为半导体衬底的高度 半导体衬底的表面，埋在半导体衬底和半导体层之间的掩埋绝缘层，以及分隔半导体层中的每个元件区域并将半导体层与半导体衬底隔离的元件隔离区域。

公开(公告)号：US20070018246A1

公开(公告)日：2007-01-25

申请号：US11447926

申请日：2006-06-07

申请人： Juri Kato ,  Hideaki Oka ,  Kei Kanemoto ,  Toshiki Hara ,  Tetsushi Sakai

发明人： Juri Kato ,  Hideaki Oka ,  Kei Kanemoto ,  Toshiki Hara ,  Tetsushi Sakai

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer, a second insulating layer formed on the first single-crystal semiconductor layer, a second single-crystal semiconductor layer formed on the second insulating layer and having a film thickness smaller than a film thickness of the first single-crystal semiconductor layer, a gate electrode formed on the second single-crystal semiconductor layer, and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.

摘要翻译： 半导体器件包括由形成在第一绝缘层上的第一单晶半导体层，形成在第一单晶半导体层上的第二绝缘层构成的背栅电极，形成在第二绝缘层上的第二单晶半导体层 并且具有比第一单晶半导体层的膜厚小的膜厚度，形成在第二单晶半导体层上的栅极电极以及形成在第二单晶半导体层上的源极和漏极层，以及 布置在栅电极的相应侧上。

公开(公告)号：US07495287B2

公开(公告)日：2009-02-24

申请号：US11649170

申请日：2007-01-03

申请人： Hideaki Oka ,  Kei Kanemoto

发明人： Hideaki Oka ,  Kei Kanemoto

IPC分类号： H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor device includes a semiconductor layer formed by epitaxial growth in a first region which is obtained by etching a semiconductor substrate to a predetermined depth, a surface of the semiconductor layer having a same height from the bottom of the semiconductor substrate as a height of a surface of the semiconductor substrate, a buried insulating layer buried between the semiconductor substrate and the semiconductor layer and an element isolation region separating each element region in the semiconductor layer and isolating the semiconductor layer from the semiconductor substrate in plan.

摘要翻译： 半导体器件包括通过在通过将半导体衬底蚀刻到预定深度而获得的第一区域中外延生长形成的半导体层，半导体层的与半导体衬底的底部相同高度的表面作为半导体衬底的高度 半导体衬底的表面，埋在半导体衬底和半导体层之间的掩埋绝缘层，以及分隔半导体层中的每个元件区域并将半导体层与半导体衬底隔离的元件隔离区域。

公开(公告)号：US20070075317A1

公开(公告)日：2007-04-05

申请号：US11489572

申请日：2006-07-20

申请人： Juri Kato ,  Hideaki Oka ,  Kei Kanemoto ,  Toshiki Hara ,  Tetsushi Sakai

发明人： Juri Kato ,  Hideaki Oka ,  Kei Kanemoto ,  Toshiki Hara ,  Tetsushi Sakai

IPC分类号： H01L29/04

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer; a second insulating layer formed on the first single-crystal semiconductor layer and having a film thickness smaller than a film thickness of the first insulating layer; a second single-crystal semiconductor layer formed on the second insulating layer; a gate electrode formed on the second single-crystal semiconductor layer; and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.

摘要翻译： 半导体器件包括由形成在第一绝缘层上的第一单晶半导体层构成的背栅电极; 形成在所述第一单晶半导体层上并具有比所述第一绝缘层的膜厚小的膜厚度的第二绝缘层; 形成在所述第二绝缘层上的第二单晶半导体层; 形成在第二单晶半导体层上的栅电极; 以及形成在第二单晶半导体层上并且布置在栅电极的相应侧上的源极和漏极层。

公开(公告)号：US20090237468A1

公开(公告)日：2009-09-24

申请号：US12407043

申请日：2009-03-19

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： B41J2/045

CPC分类号： B41J2/14233 ,  B41J2/161 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1645 ,  B41J2/1646 ,  B41J2002/1437 ,  B41J2202/18 ,  Y10T29/42 ,  Y10T29/49155 ,  Y10T29/49401

摘要： A method for manufacturing an ink jet recording head including a reservoir to which ink is supplied from outside, a pressure generating chamber leading to the reservoir, and a nozzle orifice leading to the pressure generating chamber, includes: a) forming a flow channel forming film on a first face side of a substrate having an integrated circuit; b) forming a groove in the flow channel forming film; c) filling the groove with a sacrificial film; d) forming a vibrating film on the sacrificial film and the flow channel forming film; e) forming a piezoelectric element on the vibrating film; f) forming the reservoir by etching the substrate from a second face side of the substrate to an extent where the sacrificial film is exposed; g) removing the sacrificial film through the reservoir; and h) forming the nozzle orifice in the flow channel forming film.

摘要翻译： 一种喷墨记录头的制造方法，其特征在于，包括：从外部供给墨水的储存器，通向所述储存器的压力产生室，以及通向所述压力发生室的喷嘴孔; a）形成流路形成膜 在具有集成电路的基板的第一面侧上; b）在流道形成膜中形成凹槽; c）用牺牲膜填充凹槽; d）在牺牲膜和流路形成膜上形成振动膜; e）在振动膜上形成压电元件; f）通过从衬底的第二面侧蚀刻衬底到牺牲膜暴露的程度来形成贮存器; g）通过储存器去除牺牲膜; 和h）在流道形成膜中形成喷嘴孔。

公开(公告)号：US07569438B2

公开(公告)日：2009-08-04

申请号：US11948504

申请日：2007-11-30

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/00

CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/66772

摘要： A method of manufacturing a semiconductor device that includes the steps of forming an oxide film on a surface layer section, forming a window section by selectively removing the oxide film, forming a first semiconductor layer, forming a second semiconductor layer, forming a pair of support member holes for exposing the substrate semiconductor layer, forming a support member on the active surface side of the semiconductor substrate, forming an end-exposed surface exposing at least a part of an end of the first semiconductor layer, forming a substrate semiconductor layer exposed surface, removing the first semiconductor layer below the support member by wet etching, filling a hollow section obtained by the wet etching with an oxide film using thermal oxidation, exposing the second semiconductor layer and providing a semiconductor device to the second semiconductor layer.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在表层部分上形成氧化膜，通过选择性地除去氧化膜形成窗口部分，形成第一半导体层，形成第二半导体层，形成一对支撑体 用于暴露衬底半导体层的构件孔，在半导体衬底的有源表面侧上形成支撑构件，形成露出第一半导体层的端部的至少一部分的端部暴露表面，形成衬底半导体层暴露表面 通过湿式蚀刻去除支撑构件下方的第一半导体层，用氧化膜填充通过湿蚀刻获得的中空部分，暴露第二半导体层，并向第二半导体层提供半导体器件。

公开(公告)号：US07465641B2

公开(公告)日：2008-12-16

申请号：US11393211

申请日：2006-03-29

申请人： Toshiki Hara ,  Kei Kanemoto

发明人： Toshiki Hara ,  Kei Kanemoto

IPC分类号： H01L21/76

CPC分类号： H01L21/84 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L27/1203 ,  H01L29/78684 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Manufacturing a semiconductor device by removing the insulation film in an alignment mark-forming region, depositing a first semiconductor layer, removing the insulation film on the semiconductor substrate after the second semiconductor layer is formed, forming a first exposing region for exposing the semiconductor substrate through the second semiconductor layer and the first semiconductor layer with reference to the second semiconductor layer in the alignment mark-forming region as a first alignment mark for positioning, while forming, on the semiconductor substrate, a second alignment mark, forming a second exposing region for exposing the first semiconductor layer by using the second alignment mark as a reference for positioning, forming a cavity and forming a buried insulation layer in the cavity, and forming a first grate electrode by using the second alignment mark as a reference for positioning.

摘要翻译： 通过去除对准标记形成区域中的绝缘膜来制造半导体器件，沉积第一半导体层，在形成第二半导体层之后去除半导体衬底上的绝缘膜，形成用于使半导体衬底通过的第一暴露区域 第二半导体层和第一半导体层相对于对准标记形成区域中的第二半导体层，作为第一对准标记，用于在半导体衬底上形成第二对准标记，同时在半导体衬底上形成用于定位的第二对准标记，形成用于 通过使用第二对准标记作为用于定位，形成空腔并在空腔中形成掩埋绝缘层的参考来暴露第一半导体层，并且通过使用第二对准标记作为定位的参考来形成第一栅格电极。

公开(公告)号：US07396733B2

公开(公告)日：2008-07-08

申请号：US11605588

申请日：2006-11-29

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/76

CPC分类号： H01L21/76264 ,  H01L29/66772

摘要： A method for manufacturing a semiconductor substrate, including: forming a first semiconductor layer on a semiconductive base; forming a second semiconductor layer, having a smaller etching selection ratio than that of the first semiconductor layer, on the first semiconductor layer; removing part of the first semiconductor layer and the second semiconductor layer in the vicinity of device region, so as to form a support hole that exposes the semiconductive base; forming a support forming layer on the semiconductive base, so that the support hole is buried and the second semiconductor layer is covered; leaving an region that includes the support hole and the element region, etching the rest, so that an exposed surface is formed, where a part of edges of a support, the first semiconductor layer, and of the second semiconductor layer located at the lower side of the support are exposed; forming a cavity between the second semiconductor layer and the semiconductive base by etching the first semiconductor layer through the exposed surface; forming a buried insulation layer inside the cavity; and planarizing the top side of the second semiconductor layer and removing the part of the support above the second semiconductor layer; wherein, in forming the first semiconductor layer, the first semiconductor layer is deposited with a first condition on a first region where an oxide film does not exist on the semiconductive base.

摘要翻译： 一种制造半导体衬底的方法，包括：在半导体基底上形成第一半导体层; 在所述第一半导体层上形成具有比所述第一半导体层小的蚀刻选择比的第二半导体层; 去除器件区域附近的第一半导体层和第二半导体层的一部分，以形成暴露半导电基底的支撑孔; 在所述半导体基底上形成载体形成层，使得所述支撑孔被埋置并且覆盖所述第二半导体层; 离开包括支撑孔和元件区域的区域，蚀刻其余部分，从而形成暴露表面，其中支撑体的边缘部分，第一半导体层和位于下侧的第二半导体层的一部分 的支持暴露; 通过所述暴露表面蚀刻所述第一半导体层，在所述第二半导体层和所述半导体基底之间形成空腔; 在腔内形成掩埋绝缘层; 并且平面化所述第二半导体层的顶侧并去除所述第二半导体层上方的所述支撑体的所述部分; 其中，在形成所述第一半导体层时，所述第一半导体层以第一状态沉积在半导体基底上不存在氧化膜的第一区域上。

公开(公告)号：US07326603B2

公开(公告)日：2008-02-05

申请号：US11211018

申请日：2005-08-24

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/84

CPC分类号： H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203

摘要： A semiconductor device includes a semiconductor substrate that has an oxide film selectively formed on a part thereof; a semiconductor layer that is formed on the oxide film by epitaxial growth; a first gate electrode that is formed on the semiconductor layer; first source/drain layers that are formed on the semiconductor layer so as to be disposed at both sides of the first gate electrode, respectively; a second gate electrode that is formed on the semiconductor substrate; and second source/drain layers that are formed on the semiconductor substrate so as to be disposed at both sides of the second gate electrode, respectively.

摘要翻译： 半导体器件包括：半导体衬底，其具有在其一部分上选择性地形成的氧化物膜; 通过外延生长在氧化物膜上形成的半导体层; 形成在所述半导体层上的第一栅电极; 形成在所述半导体层上以分别设置在所述第一栅电极的两侧的第一源极/漏极层; 形成在所述半导体基板上的第二栅电极; 以及第二源极/漏极层，其形成在半导体衬底上，以分别设置在第二栅电极的两侧。

公开(公告)号：US07625784B2

公开(公告)日：2009-12-01

申请号：US11820320

申请日：2007-06-19

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/00

CPC分类号： H01L21/84

摘要： The disclosure includes methods of manufacturing a semiconductor device formed on an SOI structure. In one example, a first and second semiconductor layer is formed on a semiconductor substrate including a first region. The first semiconductor layer and the second semiconductor layer are removed from a second region to form a recess for a support. A support precursor layer is formed. A portion of the support precursor layer is removed to form a support coupling the recess and the second semiconductor layer. A part of the first and second semiconductor layer is etched using the support as a mask. The first semiconductor layer is etched and removed to form a cavity under the second semiconductor layer. The second semiconductor layer is thermally oxidized to form a buried insulating layer in the cavity and the support is removed from at least the first region to expose the second semiconductor layer.

摘要翻译： 本公开包括制造形成在SOI结构上的半导体器件的方法。 在一个示例中，在包括第一区域的半导体衬底上形成第一和第二半导体层。 从第二区域去除第一半导体层和第二半导体层以形成用于支撑体的凹部。 形成支撑体前体层。 支撑前体层的一部分被去除以形成联接凹部和第二半导体层的支撑体。 使用支持体作为掩模蚀刻第一和第二半导体层的一部分。 蚀刻并去除第一半导体层以在第二半导体层下形成空腔。 第二半导体层被热氧化以在空腔中形成掩埋绝缘层，并且至少从第一区域去除载体以露出第二半导体层。